reloc.texi

这个是LINUX下的GDB调度工具的源码

(high 8 bit of data memory address) into 8 bit immediate value of
SUBI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(most high 8 bit of program memory address) into 8 bit immediate value
of LDI or SUBI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
command address) into 8 bit immediate value of LDI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
of command address) into 8 bit immediate value of LDI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
of command address) into 8 bit immediate value of LDI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(usually command address) into 8 bit immediate value of SUBI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(high 8 bit of 16 bit command address) into 8 bit immediate value
of SUBI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(high 6 bit of 22 bit command address) into 8 bit immediate
value of SUBI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_CALL
This is a 32 bit reloc for the AVR that stores 23 bit value
into 22 bits.
@end deffn
@deffn {} BFD_RELOC_390_12
Direct 12 bit.
@end deffn
@deffn {} BFD_RELOC_390_GOT12
12 bit GOT offset.
@end deffn
@deffn {} BFD_RELOC_390_PLT32
32 bit PC relative PLT address.
@end deffn
@deffn {} BFD_RELOC_390_COPY
Copy symbol at runtime.
@end deffn
@deffn {} BFD_RELOC_390_GLOB_DAT
Create GOT entry.
@end deffn
@deffn {} BFD_RELOC_390_JMP_SLOT
Create PLT entry.
@end deffn
@deffn {} BFD_RELOC_390_RELATIVE
Adjust by program base.
@end deffn
@deffn {} BFD_RELOC_390_GOTPC
32 bit PC relative offset to GOT.
@end deffn
@deffn {} BFD_RELOC_390_GOT16
16 bit GOT offset.
@end deffn
@deffn {} BFD_RELOC_390_PC16DBL
PC relative 16 bit shifted by 1.
@end deffn
@deffn {} BFD_RELOC_390_PLT16DBL
16 bit PC rel. PLT shifted by 1.
@end deffn
@deffn {} BFD_RELOC_390_PC32DBL
PC relative 32 bit shifted by 1.
@end deffn
@deffn {} BFD_RELOC_390_PLT32DBL
32 bit PC rel. PLT shifted by 1.
@end deffn
@deffn {} BFD_RELOC_390_GOTPCDBL
32 bit PC rel. GOT shifted by 1.
@end deffn
@deffn {} BFD_RELOC_390_GOT64
64 bit GOT offset.
@end deffn
@deffn {} BFD_RELOC_390_PLT64
64 bit PC relative PLT address.
@end deffn
@deffn {} BFD_RELOC_390_GOTENT
32 bit rel. offset to GOT entry.
@end deffn
@deffn {} BFD_RELOC_390_GOTOFF64
64 bit offset to GOT.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLT12
12-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLT16
16-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLT32
32-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLT64
64-bit offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_GOTPLTENT
32-bit rel. offset to symbol-entry within GOT, with PLT handling.
@end deffn
@deffn {} BFD_RELOC_390_PLTOFF16
16-bit rel. offset from the GOT to a PLT entry.
@end deffn
@deffn {} BFD_RELOC_390_PLTOFF32
32-bit rel. offset from the GOT to a PLT entry.
@end deffn
@deffn {} BFD_RELOC_390_PLTOFF64
64-bit rel. offset from the GOT to a PLT entry.
@end deffn
@deffn {} BFD_RELOC_390_TLS_LOAD
@deffnx {} BFD_RELOC_390_TLS_GDCALL
@deffnx {} BFD_RELOC_390_TLS_LDCALL
@deffnx {} BFD_RELOC_390_TLS_GD32
@deffnx {} BFD_RELOC_390_TLS_GD64
@deffnx {} BFD_RELOC_390_TLS_GOTIE12
@deffnx {} BFD_RELOC_390_TLS_GOTIE32
@deffnx {} BFD_RELOC_390_TLS_GOTIE64
@deffnx {} BFD_RELOC_390_TLS_LDM32
@deffnx {} BFD_RELOC_390_TLS_LDM64
@deffnx {} BFD_RELOC_390_TLS_IE32
@deffnx {} BFD_RELOC_390_TLS_IE64
@deffnx {} BFD_RELOC_390_TLS_IEENT
@deffnx {} BFD_RELOC_390_TLS_LE32
@deffnx {} BFD_RELOC_390_TLS_LE64
@deffnx {} BFD_RELOC_390_TLS_LDO32
@deffnx {} BFD_RELOC_390_TLS_LDO64
@deffnx {} BFD_RELOC_390_TLS_DTPMOD
@deffnx {} BFD_RELOC_390_TLS_DTPOFF
@deffnx {} BFD_RELOC_390_TLS_TPOFF
s390 tls relocations.
@end deffn
@deffn {} BFD_RELOC_390_20
@deffnx {} BFD_RELOC_390_GOT20
@deffnx {} BFD_RELOC_390_GOTPLT20
@deffnx {} BFD_RELOC_390_TLS_GOTIE20
Long displacement extension.
@end deffn
@deffn {} BFD_RELOC_IP2K_FR9
Scenix IP2K - 9-bit register number / data address
@end deffn
@deffn {} BFD_RELOC_IP2K_BANK
Scenix IP2K - 4-bit register/data bank number
@end deffn
@deffn {} BFD_RELOC_IP2K_ADDR16CJP
Scenix IP2K - low 13 bits of instruction word address
@end deffn
@deffn {} BFD_RELOC_IP2K_PAGE3
Scenix IP2K - high 3 bits of instruction word address
@end deffn
@deffn {} BFD_RELOC_IP2K_LO8DATA
@deffnx {} BFD_RELOC_IP2K_HI8DATA
@deffnx {} BFD_RELOC_IP2K_EX8DATA
Scenix IP2K - ext/low/high 8 bits of data address
@end deffn
@deffn {} BFD_RELOC_IP2K_LO8INSN
@deffnx {} BFD_RELOC_IP2K_HI8INSN
Scenix IP2K - low/high 8 bits of instruction word address
@end deffn
@deffn {} BFD_RELOC_IP2K_PC_SKIP
Scenix IP2K - even/odd PC modifier to modify snb pcl.0
@end deffn
@deffn {} BFD_RELOC_IP2K_TEXT
Scenix IP2K - 16 bit word address in text section.
@end deffn
@deffn {} BFD_RELOC_IP2K_FR_OFFSET
Scenix IP2K - 7-bit sp or dp offset
@end deffn
@deffn {} BFD_RELOC_VPE4KMATH_DATA
@deffnx {} BFD_RELOC_VPE4KMATH_INSN
Scenix VPE4K coprocessor - data/insn-space addressing
@end deffn
@deffn {} BFD_RELOC_VTABLE_INHERIT
@deffnx {} BFD_RELOC_VTABLE_ENTRY
These two relocations are used by the linker to determine which of
the entries in a C++ virtual function table are actually used.  When
the --gc-sections option is given, the linker will zero out the entries
that are not used, so that the code for those functions need not be
included in the output.

VTABLE_INHERIT is a zero-space relocation used to describe to the
linker the inheritance tree of a C++ virtual function table.  The
relocation's symbol should be the parent class' vtable, and the
relocation should be located at the child vtable.

VTABLE_ENTRY is a zero-space relocation that describes the use of a
virtual function table entry.  The reloc's symbol should refer to the
table of the class mentioned in the code.  Off of that base, an offset
describes the entry that is being used.  For Rela hosts, this offset
is stored in the reloc's addend.  For Rel hosts, we are forced to put
this offset in the reloc's section offset.
@end deffn
@deffn {} BFD_RELOC_IA64_IMM14
@deffnx {} BFD_RELOC_IA64_IMM22
@deffnx {} BFD_RELOC_IA64_IMM64
@deffnx {} BFD_RELOC_IA64_DIR32MSB
@deffnx {} BFD_RELOC_IA64_DIR32LSB
@deffnx {} BFD_RELOC_IA64_DIR64MSB
@deffnx {} BFD_RELOC_IA64_DIR64LSB
@deffnx {} BFD_RELOC_IA64_GPREL22
@deffnx {} BFD_RELOC_IA64_GPREL64I
@deffnx {} BFD_RELOC_IA64_GPREL32MSB
@deffnx {} BFD_RELOC_IA64_GPREL32LSB
@deffnx {} BFD_RELOC_IA64_GPREL64MSB
@deffnx {} BFD_RELOC_IA64_GPREL64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF22
@deffnx {} BFD_RELOC_IA64_LTOFF64I
@deffnx {} BFD_RELOC_IA64_PLTOFF22
@deffnx {} BFD_RELOC_IA64_PLTOFF64I
@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
@deffnx {} BFD_RELOC_IA64_FPTR64I
@deffnx {} BFD_RELOC_IA64_FPTR32MSB
@deffnx {} BFD_RELOC_IA64_FPTR32LSB
@deffnx {} BFD_RELOC_IA64_FPTR64MSB
@deffnx {} BFD_RELOC_IA64_FPTR64LSB
@deffnx {} BFD_RELOC_IA64_PCREL21B
@deffnx {} BFD_RELOC_IA64_PCREL21BI
@deffnx {} BFD_RELOC_IA64_PCREL21M
@deffnx {} BFD_RELOC_IA64_PCREL21F
@deffnx {} BFD_RELOC_IA64_PCREL22
@deffnx {} BFD_RELOC_IA64_PCREL60B
@deffnx {} BFD_RELOC_IA64_PCREL64I
@deffnx {} BFD_RELOC_IA64_PCREL32MSB
@deffnx {} BFD_RELOC_IA64_PCREL32LSB
@deffnx {} BFD_RELOC_IA64_PCREL64MSB
@deffnx {} BFD_RELOC_IA64_PCREL64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
@deffnx {} BFD_RELOC_IA64_SEGREL32MSB
@deffnx {} BFD_RELOC_IA64_SEGREL32LSB
@deffnx {} BFD_RELOC_IA64_SEGREL64MSB
@deffnx {} BFD_RELOC_IA64_SEGREL64LSB
@deffnx {} BFD_RELOC_IA64_SECREL32MSB
@deffnx {} BFD_RELOC_IA64_SECREL32LSB
@deffnx {} BFD_RELOC_IA64_SECREL64MSB
@deffnx {} BFD_RELOC_IA64_SECREL64LSB
@deffnx {} BFD_RELOC_IA64_REL32MSB
@deffnx {} BFD_RELOC_IA64_REL32LSB
@deffnx {} BFD_RELOC_IA64_REL64MSB
@deffnx {} BFD_RELOC_IA64_REL64LSB
@deffnx {} BFD_RELOC_IA64_LTV32MSB
@deffnx {} BFD_RELOC_IA64_LTV32LSB
@deffnx {} BFD_RELOC_IA64_LTV64MSB
@deffnx {} BFD_RELOC_IA64_LTV64LSB
@deffnx {} BFD_RELOC_IA64_IPLTMSB
@deffnx {} BFD_RELOC_IA64_IPLTLSB
@deffnx {} BFD_RELOC_IA64_COPY
@deffnx {} BFD_RELOC_IA64_LTOFF22X
@deffnx {} BFD_RELOC_IA64_LDXMOV
@deffnx {} BFD_RELOC_IA64_TPREL14
@deffnx {} BFD_RELOC_IA64_TPREL22
@deffnx {} BFD_RELOC_IA64_TPREL64I
@deffnx {} BFD_RELOC_IA64_TPREL64MSB
@deffnx {} BFD_RELOC_IA64_TPREL64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
@deffnx {} BFD_RELOC_IA64_DTPREL14
@deffnx {} BFD_RELOC_IA64_DTPREL22
@deffnx {} BFD_RELOC_IA64_DTPREL64I
@deffnx {} BFD_RELOC_IA64_DTPREL32MSB
@deffnx {} BFD_RELOC_IA64_DTPREL32LSB
@deffnx {} BFD_RELOC_IA64_DTPREL64MSB
@deffnx {} BFD_RELOC_IA64_DTPREL64LSB
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
Intel IA64 Relocations.
@end deffn
@deffn {} BFD_RELOC_M68HC11_HI8
Motorola 68HC11 reloc.
This is the 8 bit high part of an absolute address.
@end deffn
@deffn {} BFD_RELOC_M68HC11_LO8
Motorola 68HC11 reloc.
This is the 8 bit low part of an absolute address.
@end deffn
@deffn {} BFD_RELOC_M68HC11_3B
Motorola 68HC11 reloc.
This is the 3 bit of a value.
@end deffn
@deffn {} BFD_RELOC_M68HC11_RL_JUMP
Motorola 68HC11 reloc.
This reloc marks the beginning of a jump/call instruction.
It is used for linker relaxation to correctly identify beginning
of instruction and change some branches to use PC-relative
addressing mode.
@end deffn
@deffn {} BFD_RELOC_M68HC11_RL_GROUP
Motorola 68HC11 reloc.
This reloc marks a group of several instructions that gcc generates
and for which the linker relaxation pass can modify and/or remove
some of them.
@end deffn
@deffn {} BFD_RELOC_M68HC11_LO16
Motorola 68HC11 reloc.
This is the 16-bit lower part of an address.  It is used for 'call'
instruction to specify the symbol address without any special
transformation (due to memory bank window).
@end deffn
@deffn {} BFD_RELOC_M68HC11_PAGE
Motorola 68HC11 reloc.
This is a 8-bit reloc that specifies the page number of an address.
It is used by 'call' instruction to specify the page number of
the symbol.
@end deffn
@deffn {} BFD_RELOC_M68HC11_24
Motorola 68HC11 reloc.
This is a 24-bit reloc that represents the address with a 16-bit
value and a 8-bit page number.  The symbol address is transformed
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
@end deffn
@deffn {} BFD_RELOC_M68HC12_5B
Motorola 68HC12 reloc.
This is the 5 bits of a value.
@end deffn
@deffn {} BFD_RELOC_16C_NUM08
@deffnx {} BFD_RELOC_16C_NUM08_C
@deffnx {} BFD_RELOC_16C_NUM16
@deffnx {} BFD_RELOC_16C_NUM16_C
@deffnx {} BFD_RELOC_16C_NUM32
@deffnx {} BFD_RELOC_16C_NUM32_C
@deffnx {} BFD_RELOC_16C_DISP04
@deffnx {} BFD_RELOC_16C_DISP04_C
@deffnx {} BFD_RELOC_16C_DISP08
@deffnx {} BFD_RELOC_16C_DISP08_C
@deffnx {} BFD_RELOC_16C_DISP16
@deffnx {} BFD_RELOC_16C_DISP16_C
@deffnx {} BFD_RELOC_16C_DISP24
@deffnx {} BFD_RELOC_16C_DISP24_C
@deffnx {} BFD_RELOC_16C_DISP24a
@deffnx {} BFD_RELOC_16C_DISP24a_C
@deffnx {} BFD_RELOC_16C_REG04
@deffnx {} BFD_RELOC_16C_REG04_C
@deffnx {} BFD_RELOC_16C_REG04a
@deffnx {} BFD_RELOC_16C_REG04a_C
@deffnx {} BFD_RELOC_16C_REG14
@deffnx {} BFD_RELOC_16C_REG14_C
@deffnx {} BFD_RELOC_16C_REG16
@deffnx {} BFD_RELOC_16C_REG16_C
@deffnx {} BFD_RELOC_16C_REG20
@deffnx {} BFD_RELOC_16C_REG20_C
@deffnx {} BFD_RELOC_16C_ABS20
@deffnx {} BFD_RELOC_16C_ABS20_C
@deffnx {} BFD_RELOC_16C_ABS24
@deffnx {} BFD_RELOC_16C_ABS24_C
@deffnx {} BFD_RELOC_16C_IMM04
@deffnx {} BFD_RELOC_16C_IMM04_C
@deffnx {} BFD_RELOC_16C_IMM16
@deffnx {} BFD_RELOC_16C_IMM16_C
@deffnx {} BFD_RELOC_16C_IMM20
@deffnx {} BFD_RELOC_16C_IMM20_C
@deffnx {} BFD_RELOC_16C_IMM24
@deffnx {} BFD_RELOC_16C_IMM24_C
@deffnx {} BFD_RELOC_16C_IMM32
@deffnx {} BFD_RELOC_16C_IMM32_C
NS CR16C Relocations.
@end deffn
@deffn {} BFD_RELOC_CRX_REL4
@deffnx {} BFD_RELOC_CRX_REL8
@deffnx {} BFD_RELOC_CRX_REL8_CMP
@deffnx {} BFD_RELOC_CRX_REL16
@deffnx {} BFD_RELOC_CRX_REL24
@deffnx {} BFD_RELOC_CRX_REL32
@deffnx {} BFD_RELOC_CRX_REGREL12
@deffnx {} BFD_RELOC_CRX_REGREL22
@deffnx {} BFD_RELOC_CRX_REGREL28
@deffnx {} BFD_RELOC_CRX_REGREL32
@deffnx {} BFD_RELOC_CRX_ABS16
@deffnx {} BFD_RELOC_CRX_ABS32
@deffnx {} BFD_RELOC_CRX_NUM8
@deffnx {} BFD_RE