reloc.texi

这个是LINUX下的GDB调度工具的源码

@deffnx {} BFD_RELOC_SH_IMMS6BY32
@deffnx {} BFD_RELOC_SH_IMMU6
@deffnx {} BFD_RELOC_SH_IMMS10
@deffnx {} BFD_RELOC_SH_IMMS10BY2
@deffnx {} BFD_RELOC_SH_IMMS10BY4
@deffnx {} BFD_RELOC_SH_IMMS10BY8
@deffnx {} BFD_RELOC_SH_IMMS16
@deffnx {} BFD_RELOC_SH_IMMU16
@deffnx {} BFD_RELOC_SH_IMM_LOW16
@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
@deffnx {} BFD_RELOC_SH_IMM_HI16
@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
@deffnx {} BFD_RELOC_SH_PT_16
@deffnx {} BFD_RELOC_SH_TLS_GD_32
@deffnx {} BFD_RELOC_SH_TLS_LD_32
@deffnx {} BFD_RELOC_SH_TLS_LDO_32
@deffnx {} BFD_RELOC_SH_TLS_IE_32
@deffnx {} BFD_RELOC_SH_TLS_LE_32
@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32
@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32
@deffnx {} BFD_RELOC_SH_TLS_TPOFF32
Renesas / SuperH SH relocs.  Not all of these appear in object files.
@end deffn
@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH9
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
Thumb 23-, 12- and 9-bit pc-relative branches.  The lowest bit must
be zero and is not stored in the instruction.
@end deffn
@deffn {} BFD_RELOC_ARC_B22_PCREL
ARC Cores relocs.
ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
not stored in the instruction.  The high 20 bits are installed in bits 26
through 7 of the instruction.
@end deffn
@deffn {} BFD_RELOC_ARC_B26
ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
stored in the instruction.  The high 24 bits are installed in bits 23
through 0.
@end deffn
@deffn {} BFD_RELOC_D10V_10_PCREL_R
Mitsubishi D10V relocs.
This is a 10-bit reloc with the right 2 bits
assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D10V_10_PCREL_L
Mitsubishi D10V relocs.
This is a 10-bit reloc with the right 2 bits
assumed to be 0.  This is the same as the previous reloc
except it is in the left container, i.e.,
shifted left 15 bits.
@end deffn
@deffn {} BFD_RELOC_D10V_18
This is an 18-bit reloc with the right 2 bits
assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D10V_18_PCREL
This is an 18-bit reloc with the right 2 bits
assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D30V_6
Mitsubishi D30V relocs.
This is a 6-bit absolute reloc.
@end deffn
@deffn {} BFD_RELOC_D30V_9_PCREL
This is a 6-bit pc-relative reloc with
the right 3 bits assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D30V_9_PCREL_R
This is a 6-bit pc-relative reloc with
the right 3 bits assumed to be 0. Same
as the previous reloc but on the right side
of the container.
@end deffn
@deffn {} BFD_RELOC_D30V_15
This is a 12-bit absolute reloc with the
right 3 bitsassumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D30V_15_PCREL
This is a 12-bit pc-relative reloc with
the right 3 bits assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D30V_15_PCREL_R
This is a 12-bit pc-relative reloc with
the right 3 bits assumed to be 0. Same
as the previous reloc but on the right side
of the container.
@end deffn
@deffn {} BFD_RELOC_D30V_21
This is an 18-bit absolute reloc with
the right 3 bits assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D30V_21_PCREL
This is an 18-bit pc-relative reloc with
the right 3 bits assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_D30V_21_PCREL_R
This is an 18-bit pc-relative reloc with
the right 3 bits assumed to be 0. Same
as the previous reloc but on the right side
of the container.
@end deffn
@deffn {} BFD_RELOC_D30V_32
This is a 32-bit absolute reloc.
@end deffn
@deffn {} BFD_RELOC_D30V_32_PCREL
This is a 32-bit pc-relative reloc.
@end deffn
@deffn {} BFD_RELOC_DLX_HI16_S
DLX relocs
@end deffn
@deffn {} BFD_RELOC_DLX_LO16
DLX relocs
@end deffn
@deffn {} BFD_RELOC_DLX_JMP26
DLX relocs
@end deffn
@deffn {} BFD_RELOC_M32R_24
Renesas M32R (formerly Mitsubishi M32R) relocs.
This is a 24 bit absolute address.
@end deffn
@deffn {} BFD_RELOC_M32R_10_PCREL
This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_M32R_18_PCREL
This is an 18-bit reloc with the right 2 bits assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_M32R_26_PCREL
This is a 26-bit reloc with the right 2 bits assumed to be 0.
@end deffn
@deffn {} BFD_RELOC_M32R_HI16_ULO
This is a 16-bit reloc containing the high 16 bits of an address
used when the lower 16 bits are treated as unsigned.
@end deffn
@deffn {} BFD_RELOC_M32R_HI16_SLO
This is a 16-bit reloc containing the high 16 bits of an address
used when the lower 16 bits are treated as signed.
@end deffn
@deffn {} BFD_RELOC_M32R_LO16
This is a 16-bit reloc containing the lower 16 bits of an address.
@end deffn
@deffn {} BFD_RELOC_M32R_SDA16
This is a 16-bit reloc containing the small data area offset for use in
add3, load, and store instructions.
@end deffn
@deffn {} BFD_RELOC_M32R_GOT24
@deffnx {} BFD_RELOC_M32R_26_PLTREL
@deffnx {} BFD_RELOC_M32R_COPY
@deffnx {} BFD_RELOC_M32R_GLOB_DAT
@deffnx {} BFD_RELOC_M32R_JMP_SLOT
@deffnx {} BFD_RELOC_M32R_RELATIVE
@deffnx {} BFD_RELOC_M32R_GOTOFF
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO
@deffnx {} BFD_RELOC_M32R_GOTOFF_LO
@deffnx {} BFD_RELOC_M32R_GOTPC24
@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO
@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO
@deffnx {} BFD_RELOC_M32R_GOT16_LO
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO
@deffnx {} BFD_RELOC_M32R_GOTPC_LO
For PIC.
@end deffn
@deffn {} BFD_RELOC_V850_9_PCREL
This is a 9-bit reloc
@end deffn
@deffn {} BFD_RELOC_V850_22_PCREL
This is a 22-bit reloc
@end deffn
@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
This is a 16 bit offset from the short data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
This is a 16 bit offset (of which only 15 bits are used) from the
short data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
This is a 16 bit offset from the zero data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
This is a 16 bit offset (of which only 15 bits are used) from the
zero data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
This is an 8 bit offset (of which only 6 bits are used) from the
tiny data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
This is an 8bit offset (of which only 7 bits are used) from the tiny
data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
This is a 7 bit offset from the tiny data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
This is a 16 bit offset from the tiny data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
This is a 5 bit offset (of which only 4 bits are used) from the tiny
data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
This is a 4 bit offset from the tiny data area pointer.
@end deffn
@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
This is a 16 bit offset from the short data area pointer, with the
bits placed non-contiguously in the instruction.
@end deffn
@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
This is a 16 bit offset from the zero data area pointer, with the
bits placed non-contiguously in the instruction.
@end deffn
@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
This is a 6 bit offset from the call table base pointer.
@end deffn
@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
This is a 16 bit offset from the call table base pointer.
@end deffn
@deffn {} BFD_RELOC_V850_LONGCALL
Used for relaxing indirect function calls.
@end deffn
@deffn {} BFD_RELOC_V850_LONGJUMP
Used for relaxing indirect jumps.
@end deffn
@deffn {} BFD_RELOC_V850_ALIGN
Used to maintain alignment whilst relaxing.
@end deffn
@deffn {} BFD_RELOC_MN10300_32_PCREL
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
instruction.
@end deffn
@deffn {} BFD_RELOC_MN10300_16_PCREL
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
instruction.
@end deffn
@deffn {} BFD_RELOC_TIC30_LDP
This is a 8bit DP reloc for the tms320c30, where the most
significant 8 bits of a 24 bit word are placed into the least
significant 8 bits of the opcode.
@end deffn
@deffn {} BFD_RELOC_TIC54X_PARTLS7
This is a 7bit reloc for the tms320c54x, where the least
significant 7 bits of a 16 bit word are placed into the least
significant 7 bits of the opcode.
@end deffn
@deffn {} BFD_RELOC_TIC54X_PARTMS9
This is a 9bit DP reloc for the tms320c54x, where the most
significant 9 bits of a 16 bit word are placed into the least
significant 9 bits of the opcode.
@end deffn
@deffn {} BFD_RELOC_TIC54X_23
This is an extended address 23-bit reloc for the tms320c54x.
@end deffn
@deffn {} BFD_RELOC_TIC54X_16_OF_23
This is a 16-bit reloc for the tms320c54x, where the least
significant 16 bits of a 23-bit extended address are placed into
the opcode.
@end deffn
@deffn {} BFD_RELOC_TIC54X_MS7_OF_23
This is a reloc for the tms320c54x, where the most
significant 7 bits of a 23-bit extended address are placed into
the opcode.
@end deffn
@deffn {} BFD_RELOC_FR30_48
This is a 48 bit reloc for the FR30 that stores 32 bits.
@end deffn
@deffn {} BFD_RELOC_FR30_20
This is a 32 bit reloc for the FR30 that stores 20 bits split up into
two sections.
@end deffn
@deffn {} BFD_RELOC_FR30_6_IN_4
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4 bits.
@end deffn
@deffn {} BFD_RELOC_FR30_8_IN_8
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
into 8 bits.
@end deffn
@deffn {} BFD_RELOC_FR30_9_IN_8
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
into 8 bits.
@end deffn
@deffn {} BFD_RELOC_FR30_10_IN_8
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
into 8 bits.
@end deffn
@deffn {} BFD_RELOC_FR30_9_PCREL
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
short offset into 8 bits.
@end deffn
@deffn {} BFD_RELOC_FR30_12_PCREL
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
short offset into 11 bits.
@end deffn
@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
@deffnx {} BFD_RELOC_MCORE_PCREL_32
@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
@deffnx {} BFD_RELOC_MCORE_RVA
Motorola Mcore relocations.
@end deffn
@deffn {} BFD_RELOC_MMIX_GETA
@deffnx {} BFD_RELOC_MMIX_GETA_1
@deffnx {} BFD_RELOC_MMIX_GETA_2
@deffnx {} BFD_RELOC_MMIX_GETA_3
These are relocations for the GETA instruction.
@end deffn
@deffn {} BFD_RELOC_MMIX_CBRANCH
@deffnx {} BFD_RELOC_MMIX_CBRANCH_J
@deffnx {} BFD_RELOC_MMIX_CBRANCH_1
@deffnx {} BFD_RELOC_MMIX_CBRANCH_2
@deffnx {} BFD_RELOC_MMIX_CBRANCH_3
These are relocations for a conditional branch instruction.
@end deffn
@deffn {} BFD_RELOC_MMIX_PUSHJ
@deffnx {} BFD_RELOC_MMIX_PUSHJ_1
@deffnx {} BFD_RELOC_MMIX_PUSHJ_2
@deffnx {} BFD_RELOC_MMIX_PUSHJ_3
@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE
These are relocations for the PUSHJ instruction.
@end deffn
@deffn {} BFD_RELOC_MMIX_JMP
@deffnx {} BFD_RELOC_MMIX_JMP_1
@deffnx {} BFD_RELOC_MMIX_JMP_2
@deffnx {} BFD_RELOC_MMIX_JMP_3
These are relocations for the JMP instruction.
@end deffn
@deffn {} BFD_RELOC_MMIX_ADDR19
This is a relocation for a relative address as in a GETA instruction or
a branch.
@end deffn
@deffn {} BFD_RELOC_MMIX_ADDR27
This is a relocation for a relative address as in a JMP instruction.
@end deffn
@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
This is a relocation for an instruction field that may be a general
register or a value 0..255.
@end deffn
@deffn {} BFD_RELOC_MMIX_REG
This is a relocation for an instruction field that may be a general
register.
@end deffn
@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
This is a relocation for two instruction fields holding a register and
an offset, the equivalent of the relocation.
@end deffn
@deffn {} BFD_RELOC_MMIX_LOCAL
This relocation is an assertion that the expression is not allocated as
a global register.  It does not modify contents.
@end deffn
@deffn {} BFD_RELOC_AVR_7_PCREL
This is a 16 bit reloc for the AVR that stores 8 bit pc relative
short offset into 7 bits.
@end deffn
@deffn {} BFD_RELOC_AVR_13_PCREL
This is a 16 bit reloc for the AVR that stores 13 bit pc relative
short offset into 12 bits.
@end deffn
@deffn {} BFD_RELOC_AVR_16_PM
This is a 16 bit reloc for the AVR that stores 17 bit value (usually
program memory address) into 16 bits.
@end deffn
@deffn {} BFD_RELOC_AVR_LO8_LDI
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
data memory address) into 8 bit immediate value of LDI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_HI8_LDI
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
of data memory address) into 8 bit immediate value of LDI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_HH8_LDI
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
of program memory address) into 8 bit immediate value of LDI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(usually data memory address) into 8 bit immediate value of SUBI insn.
@end deffn
@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
This is a 16 bit reloc for the AVR that stores negated 8 bit value