📄 cc1100-cc2500.lst
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C51 COMPILER V7.06 CC1100_CC2500 02/03/2009 16:53:57 PAGE 12
TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1, 0x0C); // Freq synthesizer control.
TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0, 0x00); // Freq synthesizer control.
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2, 0x5D); // Freq control word, high byte
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1, 0x93); // Freq control word, mid byte.
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0, 0xB1); // Freq control word, low byte.
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4, 0x0E); // Modem configuration.
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3, 0x3B); // Modem configuration.
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2, 0x73); // Modem configuration.
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1, 0x42); // Modem configuration.
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0, 0xF8); // Modem configuration.
TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN, 0x00); // Modem dev (when FSK mod en)
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1 , 0x30); //MainRadio Cntrl State Machine
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0 , 0x18); //MainRadio Cntrl State Machine
TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG, 0x1D); // Freq Offset Compens. Config
TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG, 0x1C); // Bit synchronization config.
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control.
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1, 0x40); // AGC control.
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0, 0xB0); // AGC control.
TI_CC_SPIWriteReg(TI_CCxxx0_FREND1, 0xB6); // Front end RX configuration.
TI_CC_SPIWriteReg(TI_CCxxx0_FREND0, 0x10); // Front end RX configuration.
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3, 0xEA); // Frequency synthesizer cal.
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2, 0x0A); // Frequency synthesizer cal.
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1, 0x00); // Frequency synthesizer cal.
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0, 0x19); // Frequency synthesizer cal.
TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST, 0x59); // Frequency synthesizer cal.
TI_CC_SPIWriteReg(TI_CCxxx0_TEST2, 0x88); // Various test settings.
TI_CC_SPIWriteReg(TI_CCxxx0_TEST1, 0x31); // Various test settings.
TI_CC_SPIWriteReg(TI_CCxxx0_TEST0, 0x0B); // Various test settings.
#endif
//250K
//TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1, 0x05); // Packet automation control.
//TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0, 0x05); // Packet automation control.
//TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1, 0x07); // Freq synthesizer control.
// TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4, 0x2D); // Modem configuration.
// TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3, 0x3B); // Modem configuration.
// TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2, 0x73); // Modem configuration.
// TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN, 0x00); // Modem dev (when FSK mod en)
// TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG, 0x1D); // Freq Offset Compens. Config
//TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG, 0x1C); // Bit synchronization config.
//TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control.
//TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1, 0x00); // AGC control.
//TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control.
//TI_CC_SPIWriteReg(TI_CCxxx0_FREND1, 0xB6); // Front end RX configuration.
//TI_CC_SPIWriteReg(TI_CCxxx0_FREND0, 0x10); // Front end RX configuration.
//TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3, 0xEA); // Frequency synthesizer cal.
//单波发送
// TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1 , 0x30); //MainRadio Cntrl State Machine
// TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0 , 0x18); //MainRadio Cntrl State Machine
}
// PATABLE (0 dBm output power)
//extern char paTable[];
//extern char paTableLen ;
C51 COMPILER V7.06 CC1100_CC2500 02/03/2009 16:53:57 PAGE 13
#endif
729
730
731 //-----------------------------------------------------------------------------
732 // void RFSendPacket(char *txBuffer, char size)
733 //
734 // DESCRIPTION:
735 // This function transmits a packet with length up to 63 bytes. To use this
736 // function, GD00 must be configured to be asserted when sync word is sent and
737 // de-asserted at the end of the packet, which is accomplished by setting the
738 // IOCFG0 register to 0x06, per the CCxxxx datasheet. GDO0 goes high at
739 // packet start and returns low when complete. The function polls GDO0 to
740 // ensure packet completion before returning.
741 //
742 // ARGUMENTS:
743 // char *txBuffer
744 // Pointer to a buffer containing the data to be transmitted
745 //
746 // char size
747 // The size of the txBuffer
748 //-----------------------------------------------------------------------------
749 void RFSendPacket(char *txBuffer, char size)
750 {
751 1 TI_CC_SPIStrobe(TI_CCxxx0_SFTX); // Change state to TX, initiating
752 1 TI_CC_SPIStrobe(TI_CCxxx0_SIDLE);
753 1 TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data
754 1 TI_CC_SPIStrobe(TI_CCxxx0_STX); // Change state to TX, initiating
755 1 // data transfer
756 1
757 1 while (!(TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN));
758 1 // Wait GDO0 to go hi -> sync TX'ed//
759 1 while (TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN);
760 1 // Wait GDO0 to clear -> end of pkt//
761 1 }
762
763
764
765 //-----------------------------------------------------------------------------
766 // char RFReceivePacket(char *rxBuffer, char *length)
767 //
768 // DESCRIPTION:
769 // Receives a packet of variable length (first byte in the packet must be the
770 // length byte). The packet length should not exceed the RXFIFO size. To use
771 // this function, APPEND_STATUS in the PKTCTRL1 register must be enabled. It
772 // is assumed that the function is called after it is known that a packet has
773 // been received; for example, in response to GDO0 going low when it is
774 // configured to output packet reception status.
775 //
776 // The RXBYTES register is first read to ensure there are bytes in the FIFO.
777 // This is done because the GDO signal will go high even if the FIFO is flushed
778 // due to address filtering, CRC filtering, or packet length filtering.
779 //
780 // ARGUMENTS:
781 // char *rxBuffer
782 // Pointer to the buffer where the incoming data should be stored
783 // char *length
784 // Pointer to a variable containing the size of the buffer where the
785 // incoming data should be stored. After this function returns, that
786 // variable holds the packet length.
787 //
788 // RETURN VALUE:
789 // char
C51 COMPILER V7.06 CC1100_CC2500 02/03/2009 16:53:57 PAGE 14
790 // 0x80: CRC OK
791 // 0x00: CRC NOT OK (or no pkt was put in the RXFIFO due to filtering)
792 //-----------------------------------------------------------------------------
793 char RFReceivePacket(char *rxBuffer, char *length)
794 {
795 1 char status[2];
796 1 char pktLen;
797 1
798 1 if ((TI_CC_SPIReadStatus(TI_CCxxx0_RXBYTES) & TI_CCxxx0_NUM_RXBYTES))
799 1 {
800 2 pktLen = TI_CC_SPIReadReg(TI_CCxxx0_RXFIFO); // Read length byte
801 2
802 2 if (pktLen <= *length) // If pktLen size <= rxBuffer
803 2 {
804 3 TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, rxBuffer, pktLen); // Pull data
805 3 *length = pktLen; // Return the actual size
806 3 TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, status, 2);
807 3 // Read appended status bytes
808 3 return (char)(status[TI_CCxxx0_LQI_RX]&TI_CCxxx0_CRC_OK);
809 3 } // Return CRC_OK bit
810 2 else
811 2 {
812 3 *length = pktLen; // Return the large size
813 3 TI_CC_SPIStrobe(TI_CCxxx0_SFRX); // Flush RXFIFO
814 3 return 0; // Error
815 3 }
816 2 }
817 1 else
818 1 return 0; // Error
819 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 403 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- 13
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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