📄 ti_cc_spi.lst
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IFG2 &= ~UCA0RXIFG; // Clear flag
while (!(IFG2&UCA0RXIFG)); // Wait for end of 1st data byte TX
// First data byte now in RXBUF
for (i = 0; i < (count-1); i++)
{
UCA0TXBUF = 0; //Initiate next data RX, meanwhile..
buffer[i] = UCA0RXBUF; // Store data from last data RX
while (!(IFG2&UCA0RXIFG)); // Wait for RX to finish
}
buffer[count-1] = UCA0RXBUF; // Store last RX byte in buffer
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
char TI_CC_SPIReadStatus(char addr)
{
char x;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA0_PxIN & TI_CC_SPI_USCIA0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCA0RXIFG; // Clear flag set during last write
UCA0TXBUF = (addr | TI_CCxxx0_READ_BURST);// Send address
while (!(IFG2&UCA0RXIFG)); // Wait for TX to finish
IFG2 &= ~UCA0RXIFG; // Clear flag set during last write
UCA0TXBUF = 0; // Dummy write so we can read data
while (!(IFG2&UCA0RXIFG)); // Wait for RX to finish
x = UCA0RXBUF; // Read data
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
return x;
}
void TI_CC_SPIStrobe(char strobe)
{
IFG2 &= ~UCA0RXIFG; // Clear flag
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA0_PxIN&TI_CC_SPI_USCIA0_SOMI);// Wait for CCxxxx ready
UCA0TXBUF = strobe; // Send strobe
// Strobe addr is now being TX'ed
C51 COMPILER V7.06 TI_CC_SPI 02/03/2009 16:53:58 PAGE 9
while (!(IFG2&UCA0RXIFG)); // Wait for end of addr TX
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
void TI_CC_PowerupResetCCxxxx(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_Wait(30);
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN;
TI_CC_Wait(30);
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_Wait(45);
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA0_PxIN&TI_CC_SPI_USCIA0_SOMI);// Wait for CCxxxx ready
UCA0TXBUF = TI_CCxxx0_SRES; // Send strobe
// Strobe addr is now being TX'ed
IFG2 &= ~UCA0RXIFG; // Clear flag
while (!(IFG2&UCA0RXIFG)); // Wait for end of addr TX
while (TI_CC_SPI_USCIA0_PxIN&TI_CC_SPI_USCIA0_SOMI);
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
#elif TI_CC_RF_SER_INTF == TI_CC_SER_INTF_USCIA1
void TI_CC_SPISetup(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_CSn_PxDIR |= TI_CC_CSn_PIN; // /CS disable
UCA1CTL0 |= UCMST+UCCKPL+UCMSB+UCSYNC; // 3-pin, 8-bit SPI master
UCA1CTL1 |= UCSSEL_2; // SMCLK
UCA1BR0 |= 0x02; // UCLK/2
UCA1BR1 = 0;
UCA1MCTL = 0;
TI_CC_SPI_USCIA1_PxSEL |= TI_CC_SPI_USCIA1_SIMO | TI_CC_SPI_USCIA1_SOMI | TI_CC_SPI_USCIA1_UCLK;
// SPI option select
TI_CC_SPI_USCIA1_PxDIR |= TI_CC_SPI_USCIA1_SIMO | TI_CC_SPI_USCIA1_UCLK;
// SPI TXD out direction
UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
}
void TI_CC_SPIWriteReg(char addr, char value)
{
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA1_PxIN&TI_CC_SPI_USCIA1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCA1RXIFG; // Clear flag
UCA1TXBUF = addr; // Send address
while (!(IFG2&UCA1RXIFG)); // Wait for TX to finish
IFG2 &= ~UCA1RXIFG; // Clear flag
UCA1TXBUF = value; // Send data
while (!(IFG2&UCA1RXIFG)); // Wait for TX to finish
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
{
unsigned int i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
C51 COMPILER V7.06 TI_CC_SPI 02/03/2009 16:53:58 PAGE 10
while (TI_CC_SPI_USCIA1_PxIN&TI_CC_SPI_USCIA1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCA1RXIFG;
UCA1TXBUF = addr | TI_CCxxx0_WRITE_BURST;// Send address
while (!(IFG2&UCA1RXIFG)); // Wait for TX to finish
for (i = 0; i < count; i++)
{
IFG2 &= ~UCA1RXIFG;
UCA1TXBUF = buffer[i]; // Send data
while (!(IFG2&UCA1RXIFG)); // Wait for TX to finish
}
//while (!(IFG2&UCA1RXIFG));
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
char TI_CC_SPIReadReg(char addr)
{
char x;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (!(IFG2&UCA1TXIFG)); // Wait for TX to finish
UCA1TXBUF = (addr | TI_CCxxx0_READ_SINGLE);// Send address
while (!(IFG2&UCA1TXIFG)); // Wait for TX to finish
UCA1TXBUF = 0; // Dummy write so we can read data
// Address is now being TX'ed, with dummy byte waiting in TXBUF...
while (!(IFG2&UCA1RXIFG)); // Wait for RX to finish
// Dummy byte RX'ed during addr TX now in RXBUF
IFG2 &= ~UCA1RXIFG; // Clear flag set during addr write
while (!(IFG2&UCA1RXIFG)); // Wait for end of dummy byte TX
// Data byte RX'ed during dummy byte write is now in RXBUF
x = UCA1RXBUF; // Read data
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
return x;
}
void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
{
char i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA1_PxIN&TI_CC_SPI_USCIA1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCA1RXIFG; // Clear flag
UCA1TXBUF = (addr | TI_CCxxx0_READ_BURST);// Send address
while (!(IFG2&UCA1TXIFG)); // Wait for TXBUF ready
UCA1TXBUF = 0; // Dummy write to read 1st data byte
// Addr byte is now being TX'ed, with dummy byte to follow immediately after
while (!(IFG2&UCA1RXIFG)); // Wait for end of addr byte TX
IFG2 &= ~UCA1RXIFG; // Clear flag
while (!(IFG2&UCA1RXIFG)); // Wait for end of 1st data byte TX
// First data byte now in RXBUF
for (i = 0; i < (count-1); i++)
{
UCA1TXBUF = 0; //Initiate next data RX, meanwhile..
buffer[i] = UCA1RXBUF; // Store data from last data RX
while (!(IFG2&UCA1RXIFG)); // Wait for RX to finish
}
buffer[count-1] = UCA1RXBUF; // Store last RX byte in buffer
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
char TI_CC_SPIReadStatus(char addr)
{
C51 COMPILER V7.06 TI_CC_SPI 02/03/2009 16:53:58 PAGE 11
char x;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA1_PxIN & TI_CC_SPI_USCIA1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCA1RXIFG; // Clear flag set during last write
UCA1TXBUF = (addr | TI_CCxxx0_READ_BURST);// Send address
while (!(IFG2&UCA1RXIFG)); // Wait for TX to finish
IFG2 &= ~UCA1RXIFG; // Clear flag set during last write
UCA1TXBUF = 0; // Dummy write so we can read data
while (!(IFG2&UCA1RXIFG)); // Wait for RX to finish
x = UCA1RXBUF; // Read data
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
return x;
}
void TI_CC_SPIStrobe(char strobe)
{
IFG2 &= ~UCA1RXIFG; // Clear flag
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA1_PxIN&TI_CC_SPI_USCIA1_SOMI);// Wait for CCxxxx ready
UCA1TXBUF = strobe; // Send strobe
// Strobe addr is now being TX'ed
while (!(IFG2&UCA1RXIFG)); // Wait for end of addr TX
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
void TI_CC_PowerupResetCCxxxx(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_Wait(30);
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN;
TI_CC_Wait(30);
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_Wait(45);
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA1_PxIN&TI_CC_SPI_USCIA1_SOMI);// Wait for CCxxxx ready
UCA1TXBUF = TI_CCxxx0_SRES; // Send strobe
// Strobe addr is now being TX'ed
IFG2 &= ~UCA1RXIFG; // Clear flag
while (!(IFG2&UCA1RXIFG)); // Wait for end of addr TX
while (TI_CC_SPI_USCIA1_PxIN&TI_CC_SPI_USCIA1_SOMI);
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
#elif TI_CC_RF_SER_INTF == TI_CC_SER_INTF_USCIB0
void TI_CC_SPISetup(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_CSn_PxDIR |= TI_CC_CSn_PIN; // /CS disable
UCB0CTL0 |= UCMST+UCCKPL+UCMSB+UCSYNC; // 3-pin, 8-bit SPI master
UCB0CTL1 |= UCSSEL_2; // SMCLK
UCB0BR0 |= 0x02; // UCLK/2
UCB0BR1 = 0;
//UCB0MCTL = 0;
TI_CC_SPI_USCIB0_PxSEL |= TI_CC_SPI_USCIB0_SIMO | TI_CC_SPI_USCIB0_SOMI | TI_CC_SPI_USCIB0_UCLK;
// SPI option select
C51 COMPILER V7.06 TI_CC_SPI 02/03/2009 16:53:58 PAGE 12
TI_CC_SPI_USCIB0_PxDIR |= TI_CC_SPI_USCIB0_SIMO | TI_CC_SPI_USCIB0_UCLK;
// SPI TXD out direction
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
}
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