📄 ti_cc_spi.lst
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#elif TI_CC_RF_SER_INTF == TI_CC_SER_INTF_USART1
void TI_CC_SPISetup(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_CSn_PxDIR |= TI_CC_CSn_PIN; // /CS disable
ME2 |= USPIE1; // Enable USART1 SPI mode
UCTL1 |= CHAR + SYNC + MM; // 8-bit SPI Master **SWRST**
UTCTL1 |= CKPL + SSEL1 + SSEL0 + STC; // SMCLK, 3-pin mode
UBR01 = 0x02; // UCLK/2
UBR11 = 0x00; // 0
UMCTL1 = 0x00; // No modulation
TI_CC_SPI_USART1_PxSEL |= TI_CC_SPI_USART1_SIMO | TI_CC_SPI_USART1_SOMI | TI_CC_SPI_USART1_UCLK;
// SPI option select
TI_CC_SPI_USART1_PxDIR |= TI_CC_SPI_USART1_SIMO + TI_CC_SPI_USART1_UCLK;
// SPI TXD out direction
UCTL1 &= ~SWRST; // Initialize USART state machine
C51 COMPILER V7.06 TI_CC_SPI 02/03/2009 16:53:58 PAGE 5
}
void TI_CC_SPIWriteReg(char addr, char value)
{
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag
U1TXBUF = addr; // Send address
while (!(IFG2&URXIFG1)); // Wait for TX to finish
IFG2 &= ~URXIFG1; // Clear flag
U1TXBUF = value; // Load data for TX after addr
while (!(IFG2&URXIFG1)); // Wait for end of addr TX
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
{
char i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
U1TXBUF = addr | TI_CCxxx0_WRITE_BURST; // Send address
while (!(IFG2&UTXIFG1)); // Wait for TX to finish
for (i = 0; i < count; i++)
{
U1TXBUF = buffer[i]; // Send data
while (!(IFG2&UTXIFG1)); // Wait for TX to finish
}
IFG2 &= ~URXIFG1;
while(!(IFG2&URXIFG1));
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
char TI_CC_SPIReadReg(char addr)
{
char x;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag set during addr TX
U1TXBUF = (addr | TI_CCxxx0_READ_SINGLE); // Send address
while (!(IFG2&URXIFG1)); // Wait for TXBUF ready
IFG2 &= ~URXIFG1; // Clear flag set during addr TX
U1TXBUF = 0; // Load dummy byte for TX after addr
while (!(IFG2&URXIFG1)); // Wait for end of dummy byte TX
x = U1RXBUF; // Read data
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
return x;
}
void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
{
unsigned int i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag
U1TXBUF = (addr | TI_CCxxx0_READ_BURST); // Send address
while (!(IFG2&UTXIFG1)); // Wait for TXBUF ready
U1TXBUF = 0; // Dummy write to read 1st data byte
// Addr byte is now being TX'ed, with dummy byte to follow immediately after
C51 COMPILER V7.06 TI_CC_SPI 02/03/2009 16:53:58 PAGE 6
while (!(IFG2&URXIFG1)); // Wait for end of addr byte TX
IFG2 &= ~URXIFG1; // Clear flag
while (!(IFG2&URXIFG1)); // Wait for end of 1st data byte TX
// First data byte now in RXBUF
for (i = 0; i < (count-1); i++)
{
U1TXBUF = 0; //Initiate next data RX, meanwhile..
buffer[i] = U1RXBUF; // Store data from last data RX
while (!(IFG2&URXIFG1)); // Wait for end of data RX
}
buffer[count-1] = U1RXBUF; // Store last RX byte in buffer
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
char TI_CC_SPIReadStatus(char addr)
{
char x;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
IFG2 &= ~URXIFG1; // Clear flag set during last write
U1TXBUF = (addr | TI_CCxxx0_READ_BURST); // Send address
while (!(IFG2&URXIFG1)); // Wait for TX to finish
IFG2 &= ~URXIFG1; // Clear flag set during last write
U1TXBUF = 0; // Dummy write so we can read data
while (!(IFG2&URXIFG1)); // Wait for RX to finish
x = U1RXBUF; // Read data
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
return x;
}
void TI_CC_SPIStrobe(char strobe)
{
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
U1TXBUF = strobe; // Send strobe
// Strobe addr is now being TX'ed
IFG2 &= ~URXIFG1; // Clear flag
while (!(IFG2&URXIFG1)); // Wait for end of addr TX
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
void TI_CC_PowerupResetCCxxxx(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_Wait(30);
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN;
TI_CC_Wait(30);
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_Wait(45);
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);// Wait for CCxxxx ready
U1TXBUF = TI_CCxxx0_SRES; // Send strobe
// Strobe addr is now being TX'ed
IFG2 &= ~URXIFG1; // Clear flag
while (!(IFG2&URXIFG1)); // Wait for end of addr TX
while (TI_CC_SPI_USART1_PxIN&TI_CC_SPI_USART1_SOMI);
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
C51 COMPILER V7.06 TI_CC_SPI 02/03/2009 16:53:58 PAGE 7
#elif TI_CC_RF_SER_INTF == TI_CC_SER_INTF_USCIA0
void TI_CC_SPISetup(void)
{
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN;
TI_CC_CSn_PxDIR |= TI_CC_CSn_PIN; // /CS disable
UCA0CTL0 |= UCMST+UCCKPL+UCMSB+UCSYNC; // 3-pin, 8-bit SPI master
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 |= 0x02; // UCLK/2
UCA0BR1 = 0;
UCA0MCTL = 0;
TI_CC_SPI_USCIA0_PxSEL |= TI_CC_SPI_USCIA0_SIMO | TI_CC_SPI_USCIA0_SOMI | TI_CC_SPI_USCIA0_UCLK;
// SPI option select
TI_CC_SPI_USCIA0_PxDIR |= TI_CC_SPI_USCIA0_SIMO | TI_CC_SPI_USCIA0_UCLK;
// SPI TXD out direction
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
}
void TI_CC_SPIWriteReg(char addr, char value)
{
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA0_PxIN&TI_CC_SPI_USCIA0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCA0RXIFG; // Clear flag
UCA0TXBUF = addr; // Send address
while (!(IFG2&UCA0RXIFG)); // Wait for TX to finish
IFG2 &= ~UCA0RXIFG; // Clear flag
UCA0TXBUF = value; // Send data
while (!(IFG2&UCA0RXIFG)); // Wait for TX to finish
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
{
unsigned int i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA0_PxIN&TI_CC_SPI_USCIA0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCA0RXIFG;
UCA0TXBUF = addr | TI_CCxxx0_WRITE_BURST;// Send address
while (!(IFG2&UCA0RXIFG)); // Wait for TX to finish
for (i = 0; i < count; i++)
{
IFG2 &= ~UCA0RXIFG;
UCA0TXBUF = buffer[i]; // Send data
while (!(IFG2&UCA0RXIFG)); // Wait for TX to finish
}
//while (!(IFG2&UCA0RXIFG));
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
}
char TI_CC_SPIReadReg(char addr)
{
char x;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (!(IFG2&UCA0TXIFG)); // Wait for TX to finish
UCA0TXBUF = (addr | TI_CCxxx0_READ_SINGLE);// Send address
while (!(IFG2&UCA0TXIFG)); // Wait for TX to finish
UCA0TXBUF = 0; // Dummy write so we can read data
C51 COMPILER V7.06 TI_CC_SPI 02/03/2009 16:53:58 PAGE 8
// Address is now being TX'ed, with dummy byte waiting in TXBUF...
while (!(IFG2&UCA0RXIFG)); // Wait for RX to finish
// Dummy byte RX'ed during addr TX now in RXBUF
IFG2 &= ~UCA0RXIFG; // Clear flag set during addr write
while (!(IFG2&UCA0RXIFG)); // Wait for end of dummy byte TX
// Data byte RX'ed during dummy byte write is now in RXBUF
x = UCA0RXBUF; // Read data
TI_CC_CSn_PxOUT |= TI_CC_CSn_PIN; // /CS disable
return x;
}
void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
{
char i;
TI_CC_CSn_PxOUT &= ~TI_CC_CSn_PIN; // /CS enable
while (TI_CC_SPI_USCIA0_PxIN&TI_CC_SPI_USCIA0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCA0RXIFG; // Clear flag
UCA0TXBUF = (addr | TI_CCxxx0_READ_BURST);// Send address
while (!(IFG2&UCA0TXIFG)); // Wait for TXBUF ready
UCA0TXBUF = 0; // Dummy write to read 1st data byte
// Addr byte is now being TX'ed, with dummy byte to follow immediately after
while (!(IFG2&UCA0RXIFG)); // Wait for end of addr byte TX
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