📄 eda.map.rpt
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; I/O pins ; 11 ;
; Maximum fan-out node ; sin:u1|tmp[0] ;
; Maximum fan-out ; 24 ;
; Total fan-out ; 420 ;
; Average fan-out ; 3.47 ;
+---------------------------------------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |EDA ; 110 (0) ; 46 ; 0 ; 11 ; 0 ; 64 (0) ; 6 (0) ; 40 (0) ; 19 (0) ; 0 (0) ; |EDA ; work ;
; |delta:u2| ; 17 (17) ; 10 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 10 (10) ; 8 (8) ; 0 (0) ; |EDA|delta:u2 ; work ;
; |ladder:u4| ; 16 (16) ; 15 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 15 (15) ; 5 (5) ; 0 (0) ; |EDA|ladder:u4 ; work ;
; |setfun:u5| ; 18 (18) ; 2 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |EDA|setfun:u5 ; work ;
; |sin:u1| ; 55 (55) ; 15 ; 0 ; 0 ; 0 ; 40 (40) ; 6 (6) ; 9 (9) ; 6 (6) ; 0 (0) ; |EDA|sin:u1 ; work ;
; |square:u3| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |EDA|square:u3 ; work ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+----------------------------------------+
; ladder:u4|i[0] ; Stuck at GND due to stuck port data_in ;
; square:u3|i[0] ; Stuck at GND due to stuck port data_in ;
; delta:u2|i[0] ; Stuck at GND due to stuck port data_in ;
; sin:u1|i[0] ; Stuck at GND due to stuck port data_in ;
; ladder:u4|tmp[0..3] ; Stuck at GND due to stuck port data_in ;
; sin:u1|tem[0] ; Merged with ladder:u4|tem[0] ;
; delta:u2|tem[0] ; Merged with ladder:u4|tem[0] ;
; square:u3|tem[0] ; Merged with ladder:u4|tem[0] ;
; sin:u1|tem[1] ; Merged with ladder:u4|tem[1] ;
; delta:u2|tem[1] ; Merged with ladder:u4|tem[1] ;
; square:u3|tem[1] ; Merged with ladder:u4|tem[1] ;
; sin:u1|tem[2] ; Merged with ladder:u4|tem[2] ;
; delta:u2|tem[2] ; Merged with ladder:u4|tem[2] ;
; square:u3|tem[2] ; Merged with ladder:u4|tem[2] ;
; sin:u1|tem[3] ; Merged with ladder:u4|tem[3] ;
; delta:u2|tem[3] ; Merged with ladder:u4|tem[3] ;
; square:u3|tem[3] ; Merged with ladder:u4|tem[3] ;
; sin:u1|tem[4] ; Merged with ladder:u4|tem[4] ;
; delta:u2|tem[4] ; Merged with ladder:u4|tem[4] ;
; square:u3|tem[4] ; Merged with ladder:u4|tem[4] ;
; sin:u1|i[1] ; Merged with ladder:u4|i[1] ;
; delta:u2|i[1] ; Merged with ladder:u4|i[1] ;
; square:u3|i[1] ; Merged with ladder:u4|i[1] ;
; sin:u1|i[2] ; Merged with ladder:u4|i[2] ;
; delta:u2|i[2] ; Merged with ladder:u4|i[2] ;
; square:u3|i[2] ; Merged with ladder:u4|i[2] ;
; sin:u1|i[3] ; Merged with ladder:u4|i[3] ;
; delta:u2|i[3] ; Merged with ladder:u4|i[3] ;
; square:u3|i[3] ; Merged with ladder:u4|i[3] ;
; sin:u1|i[4] ; Merged with ladder:u4|i[4] ;
; delta:u2|i[4] ; Merged with ladder:u4|i[4] ;
; square:u3|i[4] ; Merged with ladder:u4|i[4] ;
; Total Number of Removed Registers = 35 ; ;
+----------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 46 ;
; Number of registers using Synchronous Clear ; 5 ;
; Number of registers using Synchronous Load ; 8 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 4 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |EDA|delta:u2|tmp[4] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |EDA|setfun:u5|Mux4 ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |EDA|setfun:u5|Mux1 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
Info: Processing started: Mon Jan 05 19:28:56 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EDA -c EDA
Info: Found 2 design units, including 1 entities, in source file EDA.vhd
Info: Found design unit 1: EDA-behave
Info: Found entity 1: EDA
Info: Found 2 design units, including 1 entities, in source file sin.vhd
Info: Found design unit 1: sin-behave
Info: Found entity 1: sin
Info: Found 2 design units, including 1 entities, in source file delta.vhd
Info: Found design unit 1: delta-behave
Info: Found entity 1: delta
Info: Found 2 design units, including 1 entities, in source file square.vhd
Info: Found design unit 1: square-behave
Info: Found entity 1: square
Info: Found 2 design units, including 1 entities, in source file setfun.vhd
Info: Found design unit 1: setfun-behave
Info: Found entity 1: setfun
Info: Found 2 design units, including 1 entities, in source file ladder.vhd
Info: Found design unit 1: ladder-behave
Info: Found entity 1: ladder
Info: Found 1 design units, including 1 entities, in source file MyEDA.bdf
Info: Found entity 1: MyEDA
Info: Elaborating entity "EDA" for the top level hierarchy
Info: Elaborating entity "sin" for hierarchy "sin:u1"
Info: Elaborating entity "delta" for hierarchy "delta:u2"
Info: Elaborating entity "square" for hierarchy "square:u3"
Info: Elaborating entity "ladder" for hierarchy "ladder:u4"
Info: Elaborating entity "setfun" for hierarchy "setfun:u5"
Warning (14130): Reduced register "ladder:u4|i[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "square:u3|i[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "delta:u2|i[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sin:u1|i[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ladder:u4|tmp[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ladder:u4|tmp[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ladder:u4|tmp[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "ladder:u4|tmp[3]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info (13350): Duplicate register "sin:u1|tem[0]" merged to single register "ladder:u4|tem[0]"
Info (13350): Duplicate register "delta:u2|tem[0]" merged to single register "ladder:u4|tem[0]"
Info (13350): Duplicate register "square:u3|tem[0]" merged to single register "ladder:u4|tem[0]"
Info (13350): Duplicate register "sin:u1|tem[1]" merged to single register "ladder:u4|tem[1]"
Info (13350): Duplicate register "delta:u2|tem[1]" merged to single register "ladder:u4|tem[1]"
Info (13350): Duplicate register "square:u3|tem[1]" merged to single register "ladder:u4|tem[1]"
Info (13350): Duplicate register "sin:u1|tem[2]" merged to single register "ladder:u4|tem[2]"
Info (13350): Duplicate register "delta:u2|tem[2]" merged to single register "ladder:u4|tem[2]"
Info (13350): Duplicate register "square:u3|tem[2]" merged to single register "ladder:u4|tem[2]"
Info (13350): Duplicate register "sin:u1|tem[3]" merged to single register "ladder:u4|tem[3]"
Info (13350): Duplicate register "delta:u2|tem[3]" merged to single register "ladder:u4|tem[3]"
Info (13350): Duplicate register "square:u3|tem[3]" merged to single register "ladder:u4|tem[3]"
Info (13350): Duplicate register "sin:u1|tem[4]" merged to single register "ladder:u4|tem[4]"
Info (13350): Duplicate register "delta:u2|tem[4]" merged to single register "ladder:u4|tem[4]"
Info (13350): Duplicate register "square:u3|tem[4]" merged to single register "ladder:u4|tem[4]"
Info (13350): Duplicate register "sin:u1|i[1]" merged to single register "ladder:u4|i[1]"
Info (13350): Duplicate register "delta:u2|i[1]" merged to single register "ladder:u4|i[1]"
Info (13350): Duplicate register "square:u3|i[1]" merged to single register "ladder:u4|i[1]"
Info (13350): Duplicate register "sin:u1|i[2]" merged to single register "ladder:u4|i[2]"
Info (13350): Duplicate register "delta:u2|i[2]" merged to single register "ladder:u4|i[2]"
Info (13350): Duplicate register "square:u3|i[2]" merged to single register "ladder:u4|i[2]"
Info (13350): Duplicate register "sin:u1|i[3]" merged to single register "ladder:u4|i[3]"
Info (13350): Duplicate register "delta:u2|i[3]" merged to single register "ladder:u4|i[3]"
Info (13350): Duplicate register "square:u3|i[3]" merged to single register "ladder:u4|i[3]"
Info (13350): Duplicate register "sin:u1|i[4]" merged to single register "ladder:u4|i[4]"
Info (13350): Duplicate register "delta:u2|i[4]" merged to single register "ladder:u4|i[4]"
Info (13350): Duplicate register "square:u3|i[4]" merged to single register "ladder:u4|i[4]"
Info: Implemented 121 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 8 output pins
Info: Implemented 110 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Peak virtual memory: 178 megabytes
Info: Processing ended: Mon Jan 05 19:29:10 2009
Info: Elapsed time: 00:00:14
Info: Total CPU time (on all processors): 00:00:07
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