drv_defs.h

基于S3C2440处理器的sd卡驱动程序

	RTC_HOUR,
	RTC_DAY,
	RTC_WEEK,
	RTC_MONTH,
	RTC_YEAR
} TRTC_TYPE;


/*-----------------------------------------------------------------------------
                    WATCHDOG TIMER SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define WTD_BASE    0x53000000
#define	WTCON       (*(volatile unsigned *)WTD_BASE)              /* Watchdog timer control register */
#define	WTDAT       (*(volatile unsigned *)(WTD_BASE + 0x04))     /* Watchdog timer data register */
#define	WTCNT       (*(volatile unsigned *)(WTD_BASE + 0x08))     /* Watchdog timer count register */


/*-----------------------------------------------------------------------------
                   IIC-BUS INTERFACE SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define IIC_BASE    0x54000000
#define IICCON      (*(volatile unsigned *)(IIC_BASE + 0x00))     /* IIC-Bus control register */
#define IICSTAT     (*(volatile unsigned *)(IIC_BASE + 0x04))     /* IIC-Bus control/status register */
#define IICADD      (*(volatile unsigned *)(IIC_BASE + 0x08))     /* IIC-Bus address register */
#define IICDS       (*(volatile unsigned *)(IIC_BASE + 0x0c))     /* IIC-Bus transmit/receive data shift register */
#define IICLC       (*(volatile unsigned *)(IIC_BASE + 0x10))     /* IIC-Bus multi-master line control register */


/*-----------------------------------------------------------------------------
                   IIS-BUS INTERFACE SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define IIS_BASE    0x55000000
#define IISCON      (*(volatile unsigned *)(IIS_BASE + 0x00))     /* IIS control register */
#define IISMOD      (*(volatile unsigned *)(IIS_BASE + 0x04))     /* IIS mode register */
#define IISPSR      (*(volatile unsigned *)(IIS_BASE + 0x08))     /* IIS prescaler register */
#define IISFCON     (*(volatile unsigned *)(IIS_BASE + 0x0c))     /* IIS FIFO interface register */
#define IISFIFO     (*(volatile unsigned *)(IIS_BASE + 0x10))     /* IIS FIFO register */


/*-----------------------------------------------------------------------------
                   SPI SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define SPI0_BASE   0x59000000                                    /* SPI channel 0 register base */
#define SPCON0      (*(volatile unsigned *)(SPI0_BASE + 0x00))    /* SPI channel 0 control register */
#define SPSTA0      (*(volatile unsigned *)(SPI0_BASE + 0x04))    /* SPI channel 0 status register */
#define SPPIN0      (*(volatile unsigned *)(SPI0_BASE + 0x08))    /* SPI channel 0 pin control register */
#define SPPRE0      (*(volatile unsigned *)(SPI0_BASE + 0x0c))    /* SPI cannel 0 baud rate prescaler register */
#define SPTDAT0     (*(volatile unsigned *)(SPI0_BASE + 0x10))    /* SPI channel 0 Tx data register */
#define SPRDAT0     (*(volatile unsigned *)(SPI0_BASE + 0x14))    /* SPI channel 0 Rx data register */
#define SPI1_BASE   0x59000020                                    /* SPI channel 1 register base */
#define SPCON1      (*(volatile unsigned *)(SPI1_BASE + 0x00))    /* SPI channel 1 control register */
#define SPSTA1      (*(volatile unsigned *)(SPI1_BASE + 0x04))    /* SPI channel 1 status register */
#define SPPIN1      (*(volatile unsigned *)(SPI1_BASE + 0x08))    /* SPI channel 1 pin control register */
#define SPPRE1      (*(volatile unsigned *)(SPI1_BASE + 0x0c))    /* SPI cannel 1 baud rate prescaler register */
#define SPTDAT1     (*(volatile unsigned *)(SPI1_BASE + 0x10))    /* SPI channel 1 Tx data register */
#define SPRDAT1     (*(volatile unsigned *)(SPI1_BASE + 0x14))    /* SPI channel 1 Rx data register */


/*-----------------------------------------------------------------------------
                   CAMERA INTERFACE SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define CAM_BASE         0x4F000000                                    /* CAMERA register base */
#define CISRCFMT         (*(volatile unsigned *)(CAM_BASE + 0x00))    /* Input source format register */
#define CIWDOFST         (*(volatile unsigned *)(CAM_BASE + 0x04))    /* Window offset register */
#define CIGCTRL          (*(volatile unsigned *)(CAM_BASE + 0x08))    /* Global control register */
#define CICOYSA1         (*(volatile unsigned *)(CAM_BASE + 0x18))    /* Y 1st frame start address for codec DMA */
#define CICOYSA2         (*(volatile unsigned *)(CAM_BASE + 0x1C))    /* Y 2nd frame start address for codec DMA */
#define CICOYSA3         (*(volatile unsigned *)(CAM_BASE + 0x20))    /* Y 3nd frame start address for codec DMA */
#define CICOYSA4         (*(volatile unsigned *)(CAM_BASE + 0x24))    /* Y 4th frame start address for codec DMA */
#define CICOCBSA1        (*(volatile unsigned *)(CAM_BASE + 0x28))    /* Cb 1st frame start address for codec DMA */
#define CICOCBSA2        (*(volatile unsigned *)(CAM_BASE + 0x2C))    /* Cb 2nd frame start address for codec DMA */
#define CICOCBSA3        (*(volatile unsigned *)(CAM_BASE + 0x30))    /* Cb 3nd frame start address for codec DMA */
#define CICOCBSA4        (*(volatile unsigned *)(CAM_BASE + 0x34))    /* Cb 4th frame start address for codec DMA */
#define CICOCRSA1        (*(volatile unsigned *)(CAM_BASE + 0x38))    /* Cr 1st frame start address for codec DMA */
#define CICOCRSA2        (*(volatile unsigned *)(CAM_BASE + 0x3C))    /* Cr 2nd frame start address for codec DMA */
#define CICOCRSA3        (*(volatile unsigned *)(CAM_BASE + 0x40))    /* Cr 3nd frame start address for codec DMA */
#define CICOCRSA4        (*(volatile unsigned *)(CAM_BASE + 0x44))    /* Cr 4th frame start address for codec DMA */
#define CICOTRGFMT       (*(volatile unsigned *)(CAM_BASE + 0x48))    /* Target image format of codec DMA */
#define CICOCTRL         (*(volatile unsigned *)(CAM_BASE + 0x4C))    /* Codec DMA control related */
#define CICOSCPRERATIO   (*(volatile unsigned *)(CAM_BASE + 0x50))    /* Codec pre-scaler ratio control */
#define CICOSCPREDST     (*(volatile unsigned *)(CAM_BASE + 0x54))    /* Codec pre-scaler destination format */
#define CICOSCCTRL       (*(volatile unsigned *)(CAM_BASE + 0x58))    /* Codec main-scaler control */
#define CICOTAREA        (*(volatile unsigned *)(CAM_BASE + 0x5C))    /* Codec scaler target area */
#define CICOSTATUS       (*(volatile unsigned *)(CAM_BASE + 0x64))    /* Codec path status */
#define CIPRCLRSA1       (*(volatile unsigned *)(CAM_BASE + 0x6C))    /* RGB 1st frame start address for preview DMA */
#define CIPRCLRSA2       (*(volatile unsigned *)(CAM_BASE + 0x70))    /* RGB 2nd frame start address for preview DMA */
#define CIPRCLRSA3       (*(volatile unsigned *)(CAM_BASE + 0x74))    /* RGB 3nd frame start address for preview DMA */
#define CIPRCLRSA4       (*(volatile unsigned *)(CAM_BASE + 0x78))    /* RGB 4th frame start address for preview DMA */
#define CIPRTRGFMT       (*(volatile unsigned *)(CAM_BASE + 0x7C))    /* Target image format of preview DMA */
#define CIPRCTRL         (*(volatile unsigned *)(CAM_BASE + 0x80))    /* Preview DMA control related */
#define CIPRSCPRERATIO   (*(volatile unsigned *)(CAM_BASE + 0x84))    /* Preview pre-scaler ratio control */
#define CIPRSCPREDST     (*(volatile unsigned *)(CAM_BASE + 0x88))    /* Preview pre-scaler destination format */
#define CIPRSCCTRL       (*(volatile unsigned *)(CAM_BASE + 0x8C))    /* Preview main-scaler control */
#define CIPRTAREA        (*(volatile unsigned *)(CAM_BASE + 0x90))    /* Preview scaler target area */
#define CIPRSTATUS       (*(volatile unsigned *)(CAM_BASE + 0x98))    /* Preview path status */
#define CIIMGCPT         (*(volatile unsigned *)(CAM_BASE + 0xA0))    /* Image capture enable command */


/*-----------------------------------------------------------------------------
                   PWM TIMER SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define TIMER_BASE 		0x51000000                                     /* PWM TIMER register base */
#define TCFG0 			(*(volatile unsigned *)(TIMER_BASE + 0x00))    /* TIMER CONFIGRRATION REGISTER0*/
#define TCFG1 			(*(volatile unsigned *)(TIMER_BASE + 0x04))    /* TIMER CONFIGRRATION REGISTER1*/
#define TCON 			(*(volatile unsigned *)(TIMER_BASE + 0x08))    /* TIMER CONTROL REGISTER */
#define TCNTB0 			(*(volatile unsigned *)(TIMER_BASE + 0x0c))    /* TIMER0 COUNT BUFFER REGISTER */
#define TCMPB0 			(*(volatile unsigned *)(TIMER_BASE + 0x10))    /* TIMER0 COUNT COMPARE BUFFER REGISTER */
#define TCNTO0 			(*(volatile unsigned *)(TIMER_BASE + 0x14))    /* TIMER0 COUNT OBSERVATION REGISTER */
#define TCNTB1 			(*(volatile unsigned *)(TIMER_BASE + 0x18))    /* TIMER1 COUNT BUFFER REGISTER */
#define TCMPB1 			(*(volatile unsigned *)(TIMER_BASE + 0x1c))    /* TIMER1 COUNT COMPARE BUFFER REGISTER */
#define TCNTO1 			(*(volatile unsigned *)(TIMER_BASE + 0x20))    /* TIMER1 COUNT OBSERVATION REGISTER */
#define TCNTB2 			(*(volatile unsigned *)(TIMER_BASE + 0x24))    /* TIMER2 COUNT BUFFER REGISTER */
#define TCMPB2 			(*(volatile unsigned *)(TIMER_BASE + 0x28))    /* TIMER2 COUNT COMPARE BUFFER REGISTER */
#define TCNTO2 			(*(volatile unsigned *)(TIMER_BASE + 0x2c))    /* TIMER2 COUNT OBSERVATION REGISTER */
#define TCNTB3 			(*(volatile unsigned *)(TIMER_BASE + 0x30))    /* TIMER3 COUNT BUFFER REGISTER */
#define TCMPB3 			(*(volatile unsigned *)(TIMER_BASE + 0x34))    /* TIMER3 COUNT COMPARE BUFFER REGISTER */
#define TCNTO3 			(*(volatile unsigned *)(TIMER_BASE + 0x38))    /* TIMER3 COUNT OBSERVATION REGISTER */
#define TCNTB4 			(*(volatile unsigned *)(TIMER_BASE + 0x3c))    /* TIMER4 COUNT BUFFER REGISTER */
#define TCNTO4 			(*(volatile unsigned *)(TIMER_BASE + 0x40))    /* TIMER4 COUNT OBSERVATION REGISTER */



/*-------------------------------------------------------
                   SST flash definition
--------------------------------------------------------*/
#define SST_BASE		        ((UINT16 *)0x00000000)
#define SST_END			        ((UINT16 *)0x003FFFFE)
#define SST_SECTOR_SIZE		    4096
#define SST_BLOCK_SIZE		    65536

#define SST_VENDOR_ID		    0x00BF
#define SST_PRODUCT_ID		    0x2782

#define SST_ERROR				0x01
#define SST_OK					0x00

#define FLASH_SECTOR_SIZE       0x1000





#endif  /* _DRV_DEFS_H_ */