drv_defs.h

基于S3C2440处理器的sd卡驱动程序

/*------------------------------------------------------------------------------
[BASIC]
{
	[FILENAME]  drv_defs.h 
	[CONTENT]   hardware driver register define for S3C2440A
	[AUTHOR]    xucao
	[VERSION]   01.0.00.051122
	[COMPANY]   APLUS COMMUNICATION TECHNOLOGY (BeiJing) CO.,LTD
}

[MOD]
{
	01.0.00.051120：
		1.Created initial version, defined LCD controller registers
	01.0.00.051121:
		1.add uart's define
	01.0.00.051122:
		1.add IO port register define
		2.add RTC register define
		3.add INT register and vector define
		4.add WATCHDOG TIMER register
		5.add IIC-bus register define
	01.0.00.051123:
		1.add IIS-BUS register
	01.0.00.051124:
		1.add SPI register
	01.0.00.051125:
		1.add CAMERA INTERFACE register
	01.0.00.051128：
		1.add PWM TIMER register
}

------------------------------------------------------------------------------*/

#ifndef _DRV_DEFS_H_
#define _DRV_DEFS_H_

#include "locust_defs.h"


/*-----------------------------------------------------------------------------
                    DMA SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define DMA0_BASE   0x50000000                                 /* DMA 0 registers base */
#define	DISRC0      (*(volatile unsigned *)DMA0_BASE)          /* DMA 0 initial source register */
#define	DISRCC0     (*(volatile unsigned *)(DMA0_BASE + 0x04)) /* DMA 0 initial source control register */
#define	DIDST0      (*(volatile unsigned *)(DMA0_BASE + 0x08)) /* DMA 0 initial destination register */
#define	DIDSTC0     (*(volatile unsigned *)(DMA0_BASE + 0x0c)) /* DMA 0 initial destination control register */
#define	DCON0       (*(volatile unsigned *)(DMA0_BASE + 0x10)) /* DMA 0 control register */
#define	DSTAT0      (*(volatile unsigned *)(DMA0_BASE + 0x14)) /* DMA 0 count register */
#define	DCSRC0      (*(volatile unsigned *)(DMA0_BASE + 0x18)) /* DMA 0 current source register */
#define	DCDST0      (*(volatile unsigned *)(DMA0_BASE + 0x1c)) /* DMA 0 current destination register */
#define DMASKTRIG0  (*(volatile unsigned *)(DMA0_BASE + 0x20)) /* DMA 0 mask trigger register */
#define DMA1_BASE   0x50000040                                 /* DMA 1 registers base */
#define	DISRC1      (*(volatile unsigned *)DMA0_BASE)          /* DMA 1 initial source register */
#define	DISRCC1     (*(volatile unsigned *)(DMA0_BASE + 0x04)) /* DMA 1 initial source control register */
#define	DIDST1      (*(volatile unsigned *)(DMA0_BASE + 0x08)) /* DMA 1 initial destination register */
#define	DIDSTC1     (*(volatile unsigned *)(DMA0_BASE + 0x0c)) /* DMA 1 initial destination control register */
#define	DCON1       (*(volatile unsigned *)(DMA0_BASE + 0x10)) /* DMA 1 control register */
#define	DSTAT1      (*(volatile unsigned *)(DMA0_BASE + 0x14)) /* DMA 1 count register */
#define	DCSRC1      (*(volatile unsigned *)(DMA0_BASE + 0x18)) /* DMA 1 current source register */
#define	DCDST1      (*(volatile unsigned *)(DMA0_BASE + 0x1c)) /* DMA 1 current destination register */
#define DMASKTRIG1  (*(volatile unsigned *)(DMA0_BASE + 0x20)) /* DMA 1 mask trigger register */
#define DMA2_BASE   0x50000080                                 /* DMA 2 registers base */
#define	DISRC2      (*(volatile unsigned *)DMA0_BASE)          /* DMA 2 initial source register */
#define	DISRCC2     (*(volatile unsigned *)(DMA0_BASE + 0x04)) /* DMA 2 initial source control register */
#define	DIDST2      (*(volatile unsigned *)(DMA0_BASE + 0x08)) /* DMA 2 initial destination register */
#define	DIDSTC2     (*(volatile unsigned *)(DMA0_BASE + 0x0c)) /* DMA 2 initial destination control register */
#define	DCON2       (*(volatile unsigned *)(DMA0_BASE + 0x10)) /* DMA 2 control register */
#define	DSTAT2      (*(volatile unsigned *)(DMA0_BASE + 0x14)) /* DMA 2 count register */
#define	DCSRC2      (*(volatile unsigned *)(DMA0_BASE + 0x18)) /* DMA 2 current source register */
#define	DCDST2      (*(volatile unsigned *)(DMA0_BASE + 0x1c)) /* DMA 2 current destination register */
#define DMASKTRIG2  (*(volatile unsigned *)(DMA0_BASE + 0x20)) /* DMA 2 mask trigger register */
#define DMA3_BASE   0x500000C0                                 /* DMA 3 registers base */
#define	DISRC3      (*(volatile unsigned *)DMA0_BASE)          /* DMA 3 initial source register */
#define	DISRCC3     (*(volatile unsigned *)(DMA0_BASE + 0x04)) /* DMA 3 initial source control register */
#define	DIDST3      (*(volatile unsigned *)(DMA0_BASE + 0x08)) /* DMA 3 initial destination register */
#define	DIDSTC3     (*(volatile unsigned *)(DMA0_BASE + 0x0c)) /* DMA 3 initial destination control register */
#define	DCON3       (*(volatile unsigned *)(DMA0_BASE + 0x10)) /* DMA 3 control register */
#define	DSTAT3      (*(volatile unsigned *)(DMA0_BASE + 0x14)) /* DMA 3 count register */
#define	DCSRC3      (*(volatile unsigned *)(DMA0_BASE + 0x18)) /* DMA 3 current source register */
#define	DCDST3      (*(volatile unsigned *)(DMA0_BASE + 0x1c)) /* DMA 3 current destination register */
#define DMASKTRIG3  (*(volatile unsigned *)(DMA0_BASE + 0x20)) /* DMA 3 mask trigger register */



/*-----------------------------------------------------------------------------
                    I/O PORT CONTROL SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define PORT_BASE   0x56000000                                 
#define	GPACON      (*(volatile unsigned *)PORT_BASE)          /* PORTA CONFIGURATION REGISTER */
#define GPADAT      (*(volatile unsigned *)(PORT_BASE + 0x04)) /* PORT DATA REGISTER */
#define GPBCON      (*(volatile unsigned *)(PORT_BASE + 0x10)) /* Configures the pins of port B */
#define GPBDAT      (*(volatile unsigned *)(PORT_BASE + 0x14)) /* The data register for port B */
#define GPBUP       (*(volatile unsigned *)(PORT_BASE + 0x18)) /* pull-up disable register for port B */
#define GPCCON      (*(volatile unsigned *)(PORT_BASE + 0x20)) /* Configures the pins of port C */
#define GPCDAT      (*(volatile unsigned *)(PORT_BASE + 0x24)) /* The data register for port C */
#define GPCUP       (*(volatile unsigned *)(PORT_BASE + 0x28)) /* pull-up disable register for port C */
#define GPDCON      (*(volatile unsigned *)(PORT_BASE + 0x30)) /* Configures the pins of port D */
#define GPDDAT      (*(volatile unsigned *)(PORT_BASE + 0x34)) /* The data register for port D */
#define GPDUP       (*(volatile unsigned *)(PORT_BASE + 0x38)) /* pull-up disable register for port D */
#define GPECON      (*(volatile unsigned *)(PORT_BASE + 0x40)) /* Configures the pins of port E */
#define GPEDAT      (*(volatile unsigned *)(PORT_BASE + 0x44)) /* The data register for port E */
#define GPEUP       (*(volatile unsigned *)(PORT_BASE + 0x48)) /* pull-up disable register for port E */
#define GPFCON      (*(volatile unsigned *)(PORT_BASE + 0x50)) /* Configures the pins of port F */
#define GPFDAT      (*(volatile unsigned *)(PORT_BASE + 0x54)) /* The data register for port F */
#define GPFUP       (*(volatile unsigned *)(PORT_BASE + 0x58)) /* pull-up disable register for port F */
#define GPGCON      (*(volatile unsigned *)(PORT_BASE + 0x60)) /* Configures the pins of port G */
#define GPGDAT      (*(volatile unsigned *)(PORT_BASE + 0x64)) /* The data register for port G */
#define GPGUP       (*(volatile unsigned *)(PORT_BASE + 0x68)) /* pull-up disable register for port G */
#define GPHCON      (*(volatile unsigned *)(PORT_BASE + 0x70)) /* Configures the pins of port H */
#define GPHDAT      (*(volatile unsigned *)(PORT_BASE + 0x74)) /* The data register for port H */
#define GPHUP       (*(volatile unsigned *)(PORT_BASE + 0x78)) /* pull-up disable register for port H */
#define GPJCON      (*(volatile unsigned *)(PORT_BASE + 0xD0)) /* Configures the pins of port J */
#define GPJDAT      (*(volatile unsigned *)(PORT_BASE + 0xD4)) /* The data register for port J */
#define GPJUP       (*(volatile unsigned *)(PORT_BASE + 0xD8)) /* pull-up disable register for port J */
#define MISCCR      (*(volatile unsigned *)(PORT_BASE + 0x80)) /* Miscellaneous control register */
#define DCLKCON     (*(volatile unsigned *)(PORT_BASE + 0x84)) /* DCLK0/1 Control Register */
#define EXTINT0     (*(volatile unsigned *)(PORT_BASE + 0x88)) /* External Interrupt control Register 0 */
#define EXTINT1     (*(volatile unsigned *)(PORT_BASE + 0x8C)) /* External Interrupt control Register 1 */
#define EXTINT2     (*(volatile unsigned *)(PORT_BASE + 0x90)) /* External Interrupt control Register 2 */
#define EINTFLT2    (*(volatile unsigned *)(PORT_BASE + 0x9C)) /* External Interrupt Filter Register 2 */
#define EINTFLT3    (*(volatile unsigned *)(PORT_BASE + 0xA0)) /* External Interrupt Filter Register 3 */
#define EINTMASK    (*(volatile unsigned *)(PORT_BASE + 0xA4)) /* External interupt mask Register */
#define EINTPEND    (*(volatile unsigned *)(PORT_BASE + 0xA8)) /* External interupt pending Register */
#define GSTATUS0    (*(volatile unsigned *)(PORT_BASE + 0xAC)) /* External pin status */
#define GSTATUS1    (*(volatile unsigned *)(PORT_BASE + 0xB0)) /* Chip ID */
#define GSTATUS2    (*(volatile unsigned *)(PORT_BASE + 0xB4)) /* Reset Status */
#define GSTATUS3    (*(volatile unsigned *)(PORT_BASE + 0xB8)) /* Inform register */
#define DSC0        (*(volatile unsigned *)(PORT_BASE + 0xC4)) /* strength control register 0 */
#define DSC1        (*(volatile unsigned *)(PORT_BASE + 0xC8)) /* strength control register 1 */
#define MSLCON      (*(volatile unsigned *)(PORT_BASE + 0xCC)) /* Memory Sleep Control Register */


/*-----------------------------------------------------------------------------
                    UART SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define UART0_BASE  0x50000000                                  /* UART0 registers base */
#define	ULCON0      (*(volatile unsigned *)UART0_BASE)          /* UART LINE CONTROL REGISTER */
#define	UCON0       (*(volatile unsigned *)(UART0_BASE + 0x04)) /* UART CONTROL REGISTER */
#define	UFCON0      (*(volatile unsigned *)(UART0_BASE + 0x08)) /* UART FIFO CONTROL REGISTER */
#define	UMCON0      (*(volatile unsigned *)(UART0_BASE + 0x0c)) /* UART MODEM CONTROL REGISTER */
#define	UTRSTAT0    (*(volatile unsigned *)(UART0_BASE + 0x10)) /* UART TX/RX STATUS REGISTER */
#define	UERSTAT0    (*(volatile unsigned *)(UART0_BASE + 0x14)) /* UART ERROR STATUS REGISTER */
#define	UFSTAT0     (*(volatile unsigned *)(UART0_BASE + 0x18)) /* UART FIFO STATUS REGISTER */