init.s

基于S3C2440处理器的sd卡驱动程序

;;; Copyright ARM Ltd 2001. All rights reserved.
;
; This module performs memory controller config, system clock config,and
; call cache initial, clear interrupt
; On reset, the ARM core starts up in Supervisor (SVC) mode, in ARM state, 
; with IRQ and FIQ disabled.

;  modified by xucao 2005.11.16 for S3C2440A, version:1.00

        AREA    Init, CODE, READONLY
        
                GBLL INIT_MM
INIT_MM   SETL {TRUE} ; change to {FALSE} if remapping not required


; --- ensure no functions that use semihosting SWIs are linked in from the C library

;                IMPORT __use_no_semihosting_swi
        
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled


; --- System memory locations

CM_ctl_reg      EQU     0x2001C008          ; Address of Core Module Control Register
Remap_bit       EQU     0x01                ; Bit 2 is remap bit of CM_ctl
;modify by meng
CPR_ARMCLK      EQU	0x2001C410
CPR_ZSPCLK		EQU		0x2001C414
CPR_STAR		EQU		0x2001c438	;zsp register
CPR_DSPCR		EQU		0x2001c434 	;zsp register
;CPR_ARMCLK      EQU	0x2001C410
;CPR_STAR	EQU	0x2001c430	;zsp register
;CPR_DSPCR	EQU	0x2001c42c 	;zsp register

SSC_GPIO2_DR  	EQU  	0x8001C800
SSC_GPIO2_DDR 	EQU 	0x8001C804

SSC_GPIO_MULTIPLE_REG	EQU	0x2001ED00


	ENTRY

    EXPORT  Reset_Handler

Reset_Handler
; --- arm core use asynchronous clocking mode
    MRC     p15, 0, r0, c1, c0, 0       ; read CP15 register 1 into r0
	ORR     r0, r0, #0xc0000000         ; set asynchronous clocking mode  
	MCR     p15, 0, r0, c1, c0, 0       ; write back r0 into CP15 register 1

; --- disable wacth dog timer
	LDR     r0, =0x53000000      ;WATCHDOG TIMER CONTROL REGISTER
	LDR   	r1, =0x00008000      ;disable timer and reset signal
	STR     r1, [r0]             ;save to register

; --- disable all interrupt
	LDR     r0, =0X4A000008      ;INTERRUPT MASK REGISTER
	LDR   	r1, =0xFFFFFFFF      ;mask all interrupt
	STR     r1, [r0]             ;save to register

; --- Initialize clock system
	LDR     r0, =0x4C000000      ;LOCK TIME COUNT REGISTER
	LDR   	r1, =0xFFFFFFFF      ;lock time is 300us for MCLK & UCLK
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4C000014      ;CLOCK DIVIDER CONTROL REGISTER
	LDR   	r1, =0x00000007      ;DIV OF FCLK:HCLK:PCLK=1:3:6
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4C000018      ;CAMERA CLOCK DIVIDER REGISTER
	LDR   	r1, =0x00000010      ;DVS OFF,HCLK = FCLK/3,Camera clock = UPLL/2
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4C000004      ;PLL CONTROL REGISTER for MPLL
	LDR   	r1, =0x0006E031      ;IN 16.9344M, OUT 399.65M, MDIV=0x6E, PDIV=3, SDIV=1 ;For Demo board
;	LDR   	r1, =0x0007F021      ;IN 12.0000M, OUT 405.00M, MDIV=0x7F, PDIV=2, SDIV=1 ;For Aplus board
	STR     r1, [r0]             ;save to register
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP

	LDR     r0, =0x4C000008      ;PLL CONTROL REGISTER for UPLL
	LDR   	r1, =0x0003C042      ;IN 16.9344M, OUT 47.98M,  MDIV=0x3C, PDIV=4, SDIV=2 ;For Demo board
;	LDR   	r1, =0x00038021      ;IN 12.0000M, OUT 48.00M,  MDIV=0x38, PDIV=2, SDIV=1 ;For Aplus board
	STR     r1, [r0]             ;save to register
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP

	LDR     r0, =0x4C00000C      ;CLOCK CONTROL REGISTER
	LDR   	r1, =0x00FFFFF0      ;Enable:  Camera SPI IIS RTC GPIO UART1 UART0 SDI PWMTIMER USB_device LCDC NAND_Flash_Controller
	                             ;Disable: AC97 IIC ADC UART2 USB_host
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4C000010      ;CLOCK SLOW CONTROL REGISTER for MULL
	LDR   	r1, =0x00000004      ;U&M PLL ON,FCLK = Mpll (MPLL output)
	STR     r1, [r0]             ;save to register

;delay after config
	LDR 	r1, =0x0100
1
	SUB		r1, r1, #4
	CMP     r1, #0
	BNE		%B1
 
; --- Initialize memory system
   	LDR     r0, =0x48000000      ;BUS WIDTH & WAIT CONTROL register
	LDR   	r1, [r0]             ;read the register
	AND     r1, r1, #0xF0FFFFFF  ;clear CS6 set
	ORR     r1, r1, #0x02000000  ;32bit, no wait, nWBE[3:0]
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x48000004      ;BANK0 CONTROL register for flash
	LDR   	r1, =0x00000700      ;Tacs=0, Tcos=0, Tacc=14, Tcoh=0, Tcah=0, Tacp=0, PMC=0
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4800001C      ;BANK6 CONTROL register for SDRAM
	LDR   	r1, =0x00018005      ;MT=11, RAS to CAS = 3, Column address number = 9bit
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x48000024      ;REFRESH CONTROL register for SDRAM
	LDR   	r1, =0x009C03F3      ;Enable refresh, CBR/Auto Refresh, Trp = 3, Tsrc = 7clk 
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x48000028      ;BANK SIZE register for SDRAM
	LDR   	r1, =0x00000082      ;Enable ARM core burst, 128M 
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4800002C      ;SDRAM MODE REGISTER SET register for SDRAM
	LDR   	r1, =0x00000030      ;CAS = 3 
	STR     r1, [r0]             ;save to register
;delay after config
	LDR 	r1, =0x0100
1
	SUB		r1, r1, #4
	CMP     r1, #0
	BNE		%B1
 		

; --- Initialize critical IO devices


           
; transit RO RW ZI segment data
	IMPORT	TCT_Transit_Code
	BL	TCT_Transit_Code

; move resource data from flash to sdram
;	IMPORT 	move_resource
;	BL move_resource


; --- Now enter the RTOS code
    IMPORT  INT_Initialize
    B       INT_Initialize   ; note use B not BL, because an application will never return this way



        END