common.h

ppp拨号程序源代码采用atmel芯片c语言编

/*
 * Copyright (C) 2003-2004 by Clive Moss. Email [e-mail] All rights reserved.
 *
 * Help & Contributions from D.J.Armstrong Email [e-mail]
 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY CLIVE MOSS 'AS IS' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.
 * IN NO EVENT SHALL CLIVE MOSS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL,SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#ifndef commonH
#define commonH

// *********************************************************************************
// compile options

#if defined(__IMAGECRAFT__)
#define CPU_ATmega128
#else
//#if defined(_Z8F640) || defined(_Z8F642)
#define CPU_eZ8
//#endif
#endif

#define Debug										// comment this out to compile without the debug info (debug text sent to the console)

#define ConsoleHandShaking							// comment this out if you don't want console uart hardware handshaking (RTS/CTS)
#define ModemHandShaking							// comment this out if you don't want ppp uart hardware handshaking (RTS/CTS)

// PPP mode to use - ONLY one of these must be used
#define WindowsPPP									//
//#define ATModemPPP									//
//#define GPRS_Orange									//
//#define GPRS_VodaPhone								//

#define IncludeICMP										// include the ICMP code
//#define IncludeUDP										// include the UDP code
//#define IncludeNTP										// include the NTP code
#define IncludeTCP										// include the TCP code

#define StaticTCPSocket								// if this is defined, we use a static TCP socket in memory - ie, not allocated from the heap

// *********************************************************************************

#ifdef CPU_eZ8
	#include <eZ8.h>
	
    #define flash rom    
#endif	

#ifdef CPU_ATmega128
	#include <iom128v.h>
	#include <macros.h>
	
    #define flash const    
#endif

// *********************************************************************************
// basic data types

#define true					1
#define false					0

typedef unsigned char			bool;		// 1-byte
typedef unsigned char			u8;			// 1-byte 0..255
typedef signed char			s8;			// 1-byte -128..127

#ifdef CPU_eZ8
typedef unsigned short			u16;		// 2-bytes 0..65535
typedef signed short			s16;		// 2-bytes -32768..32767
typedef unsigned long			u32;		// 4-bytes 0..4294967295
typedef signed long			s32;		// 4-bytes -2147483648..2147483647
#endif

#ifdef CPU_ATmega128
typedef unsigned short			u16;
typedef short					s16;
typedef unsigned long			u32;
typedef long					s32;
//typedef long long				s64;
//typedef unsigned long long		u64;
#endif

// *********************************************************************************
// various defines

#define MainBufferSize	512			//

#define WatchdogTimeout	100000		// 20us increments - 100,000 = 2000ms seconds

#ifdef CPU_eZ8
#define MainClk			18432000	// xtal osc freq
#endif
#ifdef CPU_ATmega128
#define MainClk			7372800		// xtal osc freq
#endif

#define UART0			0
#define UART1			1

#define UART0_BaudRate	115200
#define UART1_BaudRate	19200

#define ConsoleUart		UART0
#define ModemUart		UART1

#ifdef CPU_eZ8
#define TimerIntSpeed	1440		// 10ms timer interrupt ((MainClk / 128) / 1440) = 100 ints per second
#endif
#ifdef CPU_ATmega128
#define TimerIntSpeed	0xdc00		// 10ms timer interrupt ((MainClk / 8) / 9216) = 100 ints per second ... 0xdc00 = -9216
#endif

#define button_debounce	8			// 80ms push button debounce

#define	MPH_2_KNOTS		1.1507771555 
#define	KNOTS_2_MPH		0.868978 

#define	KNOTS_2_KM		2.478322 
#define	KM_2_KNOTS		0.4034988 

#define	MPH_2_KM		1.609344
#define	KM_2_MPH		0.6213711

// *********************************************************************************
// Macros

#ifdef CPU_eZ8
#define Disable_Ints()	DI()						// disable global interrupts
#endif
#ifdef CPU_ATmega128
#define Disable_Ints()	CLI()						// disable global interrupts
#endif

#ifdef CPU_eZ8
#define Enable_Ints()	EI()						// Enable global Interrupts
#endif
#ifdef CPU_ATmega128
#define Enable_Ints()	SEI()						// enable global interrupts
#endif

#define ByteSwap2(val)				\
    (((val & 0xff) << 8) |			\
     ((val & 0xff00) >> 8))

#define ByteSwap4(val)				\
    (((val & 0xff) << 24) |			\
     ((val & 0xff00) << 8) |		\
     ((val & 0xff0000) >> 8) |		\
     ((val & 0xff000000) >> 24))

#ifdef CPU_eZ8
//#define	Reset_WD()	WDT;									// reset the watchdog - the zilog compiler ignores this
#define	Reset_WD()	asm("WDT");								// so do it our selves
#endif
#ifdef CPU_ATmega128
#define	Reset_WD()	WDR()
#endif

#ifdef CPU_eZ8
#define RomChar	char rom
#endif
#ifdef CPU_ATmega128
#define RomChar	const char
#endif

// *********************************************************************************
// pins

#ifdef CPU_eZ8

#define RLed_addrPort		PAADDR	// address
#define RLed_oPort			PAOUT	// output
#define RLed_afPort			PAAF	// alternate function
#define RLed_ocPort			PAOC	// output control
#define RLed_ddPort			PADD	// direction
#define RLed_hdePort		PAHDE	// high drive
#define RLed_iPort			PAIN	// input
#define RLed_Pin			0		// bit

#define YLed_addrPort		PAADDR	// address
#define YLed_oPort			PAOUT	// output
#define YLed_afPort			PAAF	// alternate function
#define YLed_ocPort			PAOC	// output control
#define YLed_ddPort			PADD	// direction
#define YLed_hdePort		PAHDE	// high drive
#define YLed_iPort			PAIN	// input
#define YLed_Pin			1		// bit

#define GLed_addrPort		PAADDR	// address
#define GLed_oPort			PAOUT	// output
#define GLed_afPort			PAAF	// alternate function
#define GLed_ocPort			PAOC	// output control
#define GLed_ddPort			PADD	// direction
#define GLed_hdePort		PAHDE	// high drive
#define GLed_iPort			PAIN	// input
#define GLed_Pin			2		// bit

#define TestBut_addrPort	PCADDR	// address
#define TestBut_oPort		PCOUT	// output
#define TestBut_afPort		PCAF	// alternate function
#define TestBut_ocPort		PCOC	// output control
#define TestBut_ddPort		PCDD	// direction
#define TestBut_hdePort		PCHDE	// high drive
#define TestBut_iPort		PCIN	// input
#define TestBut_Pin			0		// bit

#define SS_addrPort			PCADDR	// address
#define SS_oPort			PCOUT	// output
#define SS_afPort			PCAF	// alternate function
#define SS_ocPort			PCOC	// output control
#define SS_ddPort			PCDD	// direction
#define SS_hdePort			PCHDE	// high drive
#define SS_iPort			PCIN	// input
#define SS_Pin				2		// bit

#define SCLK_addrPort		PCADDR	// address
#define SCLK_oPort			PCOUT	// output
#define SCLK_afPort			PCAF	// alternate function
#define SCLK_ocPort			PCOC	// output control
#define SCLK_ddPort			PCDD	// direction
#define SCLK_hdePort		PCHDE	// high drive
#define SCLK_iPort			PCIN	// input
#define SCLK_Pin			3		// bit

#define MOSI_addrPort		PCADDR	// address
#define MOSI_oPort			PCOUT	// output
#define MOSI_afPort			PCAF	// alternate function
#define MOSI_ocPort			PCOC	// output control
#define MOSI_ddPort			PCDD	// direction
#define MOSI_hdePort		PCHDE	// high drive
#define MOSI_iPort			PCIN	// input
#define MOSI_Pin			4		// bit

#define MISO_addrPort		PCADDR	// address
#define MISO_oPort			PCOUT	// output
#define MISO_afPort			PCAF	// alternate function
#define MISO_ocPort			PCOC	// output control
#define MISO_ddPort			PCDD	// direction
#define MISO_hdePort		PCHDE	// high drive
#define MISO_iPort			PCIN	// input
#define MISO_Pin			5		// bit

#define CTS0_addrPort		PAADDR	// address
#define CTS0_oPort			PAOUT	// output
#define CTS0_afPort			PAAF	// alternate function
#define CTS0_ocPort			PAOC	// output control
#define CTS0_ddPort			PADD	// direction
#define CTS0_hdePort		PAHDE	// high drive
#define CTS0_iPort			PAIN	// input
#define CTS0_Pin			3		// bit

#define RTS0_addrPort		PDADDR	// address
#define RTS0_oPort			PDOUT	// output
#define RTS0_afPort			PDAF	// alternate function
#define RTS0_ocPort			PDOC	// output control
#define RTS0_ddPort			PDDD	// direction
#define RTS0_hdePort		PDHDE	// high drive
#define RTS0_iPort			PDIN	// input
#define RTS0_Pin			1		// bit

#define TXD0_addrPort		PAADDR	// address
#define TXD0_oPort			PAOUT	// output
#define TXD0_afPort			PAAF	// alternate function
#define TXD0_ocPort			PAOC	// output control
#define TXD0_ddPort			PADD	// direction
#define TXD0_hdePort		PAHDE	// high drive
#define TXD0_iPort			PAIN	// input
#define TXD0_Pin			5		// bit

#define CTS1_addrPort		PDADDR	// address
#define CTS1_oPort			PDOUT	// output
#define CTS1_afPort			PDAF	// alternate function
#define CTS1_ocPort			PDOC	// output control
#define CTS1_ddPort			PDDD	// direction
#define CTS1_hdePort		PDHDE	// high drive
#define CTS1_iPort			PDIN	// input
#define CTS1_Pin			6		// bit

#define RTS1_addrPort		PDADDR	// address
#define RTS1_oPort			PDOUT	// output
#define RTS1_afPort			PDAF	// alternate function
#define RTS1_ocPort			PDOC	// output control
#define RTS1_ddPort			PDDD	// direction
#define RTS1_hdePort		PDHDE	// high drive
#define RTS1_iPort			PDIN	// input
#define RTS1_Pin			0		// bit

#define TXD1_addrPort		PDADDR	// address
#define TXD1_oPort			PDOUT	// output
#define TXD1_afPort			PDAF	// alternate function
#define TXD1_ocPort			PDOC	// output control
#define TXD1_ddPort			PDDD	// direction
#define TXD1_hdePort		PDHDE	// high drive
#define TXD1_iPort			PDIN	// input
#define TXD1_Pin			5		// bit

#endif

#ifdef CPU_ATmega128

#define RLed_iPort			PINB	// input
#define RLed_oPort			PORTB	// output
#define RLed_ddPort			DDRB	// data direction
#define RLed_Pin			5		//

#define YLed_iPort			PINB	// input
#define YLed_oPort			PORTB	// output
#define YLed_ddPort			DDRB	// data direction
#define YLed_Pin			6		//

#define GLed_iPort			PINB	// input
#define GLed_oPort			PORTB	// output
#define GLed_ddPort			DDRB	// data direction
#define GLed_Pin			7		//

#define TestBut_iPort		PIND	// input
#define TestBut_oPort		PORTD	// output
#define TestBut_ddPort		DDRD	// data direction
#define TestBut_Pin			0		//

#define SS_iPort			PINB	// input
#define SS_oPort			PORTB	// output
#define SS_ddPort			DDRB	// data direction
#define SS_Pin				0		//

#define SCLK_iPort			PINB	// input
#define SCLK_oPort			PORTB	// output
#define SCLK_ddPort			DDRB	// data direction
#define SCLK_Pin			1		//

#define MOSI_iPort			PINB	// input
#define MOSI_oPort			PORTB	// output
#define MOSI_ddPort			DDRB	// data direction
#define MOSI_Pin			2		//

#define MISO_iPort			PINB	// input
#define MISO_oPort			PORTB	// output
#define MISO_ddPort			DDRB	// data direction
#define MISO_Pin			3		//

#define TXD0_iPort			PINE	// input
#define TXD0_oPort			PORTE	// output
#define TXD0_ddPort			DDRE	// data direction
#define TXD0_Pin			1		//

#define CTS0_iPort			PINE	// input
#define CTS0_oPort			PORTE	// output
#define CTS0_ddPort			DDRE	// data direction
#define CTS0_Pin			2		//

#define RTS0_iPort			PINE	// input
#define RTS0_oPort			PORTE	// output
#define RTS0_ddPort		DDRE	// data direction
#define RTS0_Pin			3		//

#define TXD1_iPort			PIND	// input
#define TXD1_oPort			PORTD	// output