init.asm

uCosII是一个小型的多任务调度内核

;;; Copyright ARM Ltd 2001. All rights reserved.
;
; This module performs memory controller config, system clock config,and
; call cache initial, clear interrupt
; On reset, the ARM core starts up in Supervisor (SVC) mode, in ARM state, 
; with IRQ and FIQ disabled.
;*****************************************************************************

       
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled

 
	AREA    Init, CODE, READONLY
	ENTRY

    EXPORT  Reset_Handler

Reset_Handler
; --- arm core use asynchronous clocking mode
	MRC     p15, 0, r0, c1, c0, 0       ; read CP15 register 1 into r0
	ORR     r0, r0, #0xc0000000         ; set asynchronous clocking mode  
	MCR     p15, 0, r0, c1, c0, 0       ; write  back r0 into CP15 register 1

; --- disable wacth dog timer
	LDR     r0, =0x53000000      ;WATCHDOG TIMER CONTROL REGISTER
	LDR   	r1, =0x00008000      ;disable timer and reset signal
	STR     r1, [r0]             ;save to register

; --- disable all interrupt
	LDR     r0, =0x4A000008      ;INTERRUPT MASK REGISTER
	LDR   	r1, =0xFFFFFFFF      ;mask all interrupt
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4A000000      ;INTERRUPT MASK REGISTER
	STR     r1, [r0]             ;clear suspend int
	ADD     r0, r0, #0x10        ;INTERRUPT MASK REGISTER
	STR     r1, [r0]             ;clear now suspenint

; --- Initialize clock system
	LDR     r0, =0x4C000000      ;LOCK TIME COUNT REGISTER
	LDR   	r1, =0xFFFFFFFF      ;lock time is 300us for MCLK & UCLK
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4C000014      ;CLOCK DIVIDER CONTROL REGISTER
;	LDR   	r1, =0x00000001      ;DIV OF FCLK:HCLK:PCLK=1:1:2 
;	LDR   	r1, =0x00000002      ;DIV OF FCLK:HCLK:PCLK=1:2:2 
	LDR   	r1, =0x00000003      ;DIV OF FCLK:HCLK:PCLK=1:2:4
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4C000004      ;PLL CONTROL REGISTER for MPLL
	LDR   	r1, =0x000a1031      ;IN 12.0000M, OUT 202.80M, MDIV=0xA1, PDIV=3, SDIV=1 ;For S3C2410 board
	STR     r1, [r0]             ;save to register
	NOP
	NOP
	NOP
	NOP

	LDR     r0, =0x4C000008      ;PLL CONTROL REGISTER for UPLL
	LDR   	r1, =0x00078023      ;IN 12.0000M, OUT 48.00M,  MDIV=0x78, PDIV=2, SDIV=3 ;For S3C2410 board
	STR     r1, [r0]             ;save to register
	NOP
	NOP
	NOP
	NOP

	LDR     r0, =0x4C00000C      ;CLOCK CONTROL REGISTER
	LDR   	r1, =0x0007FFF0      ;Enable all
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4C000010      ;CLOCK SLOW CONTROL REGISTER for MULL
	LDR   	r1, =0x00000004      ;U&M PLL ON,FCLK = Mpll (MPLL output)
	STR     r1, [r0]             ;save to register

;delay after config
	LDR 	r1, =0x0100
1
	SUB		r1, r1, #4
	CMP     r1, #0
	BNE		%B1

;	BL      Sdram_init
           
; transit RO RW ZI segment data
;	IMPORT	TCT_Transit_Code
;	BL	TCT_Transit_Code


; move resource data from flash to sdram
;	IMPORT 	move_resource
;	BL move_resource

	IMPORT Cache_Init
	BL Cache_Init

; --- Now enter the RTOS code
	IMPORT OS_Initialize
	B OS_Initialize

;******************************************************************************
;	void Sdram_init
;******************************************************************************
Sdram_init
; --- Initialize memory system
   	LDR     r0, =0x48000000      ;BUS WIDTH & WAIT CONTROL register
	LDR   	r1, [r0]             ;read the register
	AND     r1, r1, #0xF0FFFFFF  ;clear CS6 set
	ORR     r1, r1, #0x02000000  ;32bit, no wait, nWBE[3:0]
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x48000004      ;BANK0 CONTROL register for flash
	LDR   	r1, =0x00000700      ;Tacs=0, Tcos=0, Tacc=14, Tcoh=0, Tcah=0, Tacp=0, PMC=0
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4800001C      ;BANK6 CONTROL register for SDRAM
;	LDR   	r1, =0x00018005      ;MT=11, RAS to CAS = 3, Column address number = 9bit  ;for Demo board
	LDR   	r1, =0x00018004      ;MT=11, RAS to CAS = 4, Column address number = 8bit  ;for Aplus board
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x48000024      ;REFRESH CONTROL register for SDRAM
;	LDR   	r1, =0x009C03F3      ;Enable refresh, CBR/Auto Refresh, Trp = 3, Tsrc = 7clk 
	LDR   	r1, =0x009C03F3      ;Enable refresh, CBR/Auto Refresh, Trp = 3, Tsrc = 7clk 
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x48000028      ;BANK SIZE register for SDRAM
;	LDR   	r1, =0x00000082      ;Enable ARM core burst, 128M for demo board
	LDR   	r1, =0x00000086      ;Enable ARM core burst,   8M for APlus board
	STR     r1, [r0]             ;save to register

	LDR     r0, =0x4800002C      ;SDRAM MODE REGISTER SET register for SDRAM
	LDR   	r1, =0x00000030      ;CAS = 3 
	STR     r1, [r0]             ;save to register
;delay after config
	LDR 	r1, =0x0100
1
	SUB		r1, r1, #4
	CMP     r1, #0
	BNE		%B1
 		


	END