📄 drv_defs.h
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#define IISCON_CH_LEFT (0 << 8) /* Left channel */
#define IISCON_TX_RDY (1 << 7) /* Transmit FIFO is ready(not empty) */
#define IISCON_RX_RDY (1 << 6) /* Receive FIFO is ready (not full) */
#define IISCON_TX_DMA (1 << 5) /* Transmit DMA service reqeust */
#define IISCON_RX_DMA (1 << 4) /* Receive DMA service reqeust */
#define IISCON_TX_IDLE (1 << 3) /* Transmit Channel idle */
#define IISCON_RX_IDLE (1 << 2) /* Receive Channel idle */
#define IISCON_PRESCALE (1 << 1) /* IIS Prescaler Enable */
#define IISCON_EN (1 << 0) /* IIS enable(start) */
#define IISMOD_SEL_PCLK (0 << 9) /* PCLK as Master Clock */
#define IISMOD_SEL_MPLLIN (1 << 9) /* MPLLin as Master Clock */
#define IISMOD_SEL_MA (0 << 8) /* Master mode (IISLRCK, IISCLK are Output) */
#define IISMOD_SEL_SL (1 << 8) /* Slave mode (IISLRCK, IISCLK are Input) */
#define IISMOD_SEL_NO (0 << 6) /* No Transfer */
#define IISMOD_SEL_RX (1 << 6) /* Receive */
#define IISMOD_SEL_TX (2 << 6) /* Transmit */
#define IISMOD_SEL_BOTH (3 << 6) /* Tx & Rx */
#define IISMOD_CH_RIGHT (0 << 5) /* high for right channel */
#define IISMOD_CH_LEFT (1 << 5) /* high for left channel */
#define IISMOD_FMT_IIS (0 << 4) /* IIS-compatible format */
#define IISMOD_FMT_MSB (1 << 4) /* MSB(left)-justified format */
#define IISMOD_BIT_8 (0 << 3) /* Serial data bit/channel is 8 bit*/
#define IISMOD_BIT_16 (1 << 3) /* Serial data bit/channel is 16 bit*/
#define IISMOD_FREQ_256 (0 << 2) /* Master clock freq = 256 fs */
#define IISMOD_FREQ_384 (1 << 2) /* Master clock freq = 384 fs */
#define IISMOD_SFREQ_16 (0) /* 16 fs */
#define IISMOD_SFREQ_32 (1) /* 32 fs */
#define IISMOD_SFREQ_48 (2) /* 48 fs */
#define IISPSR_A(x) (x<<5) /* internal clock prescaler */
#define IISPSR_B(x) (x) /* external clock prescaler */
#define IISFCON_TX_NORM (0 << 15) /* Transmit FIFO access mode: normal */
#define IISFCON_TX_DMA (1 << 15) /* Transmit FIFO access mode: DMA */
#define IISFCON_RX_NORM (0 << 14) /* Receive FIFO access mode: normal */
#define IISFCON_RX_DMA (1 << 14) /* Receive FIFO access mode: DMA */
#define IISFCON_TX_EN (1 << 13) /* Transmit FIFO enable */
#define IISFCON_RX_EN (1 << 12) /* Recevice FIFO enable */
#define IISFCON_TX_CNT /* Tx FIFO data count (Read-Only) */
#define IISFCON_RX_CNT /* Rx FIFO data count (Read-Only) */
#if (DIGITAL_APLUS_V1_1\
|DIGITAL_APLUS_V1_2\
|DIGITAL_APLUS_V1\
|DIGITAL_APLUS_V1_1062\
|DIGITAL_APLUS_V1_5\
|DIGITAL_APLUS_V1_61\
|DIGITAL_APLUS_V1_70\
|DIGITAL_APLUS_V2\
|DIGITAL_APLUS_V1_41\
|DIGITAL_APLUS_920)
enum __AUC_MODE_STRUCT{
AUC_NONE,
AUC_WRITE,
AUC_READ,
AUC_RDWR,
AUC_PHONE,
AUC_MODE_END
};
typedef enum __AUC_MODE_STRUCT AUC_MODE_T;
enum __AUC_FS_STRUCT{
AUC_FS_8K = 8000,
AUC_FS_11K = 11025,
AUC_FS_16K = 16000,
AUC_FS_22K = 22050,
AUC_FS_44K = 44100,
AUC_FS_END
};
typedef enum __AUC_FS_STRUCT AUC_FS_T;
enum __AUC_PARAM_STRUCT{
AUC_DEFAULT,
AUC_HS_MIC,
AUC_HF_MIC,
AUC_HS_SPK,
AUC_HF_SPK,
AUC_HS_ANALOG,
AUC_HF_ANALOG,
AUC_HS_VIDEO,
AUC_HF_VIDEO,
AUC_MUTE_SPK,
AUC_MUTE_ALL,
};
typedef enum __AUC_PARAM_STRUCT AUC_PARAM_T;
enum __AUC_CHANNEL_STRUCT{
AUC_MONO =0,
AUC_STERO
};
typedef enum __AUC_CHANNEL_STRUCT AUC_CHANNEL_T;
/* -----------------------------Define macros-------------------------------- */
#define DEFAULT_CH AUC_MONO
#define DEFAULT_FS AUC_FS_8K
#define DEFAULT_M_CLK 384
#if SDRAM_100M
#define __PCLK 50625000
#elif SDRAM_133M
#define __PCLK 67500000
#endif
#define __HISR_ST_SIZE 0x400
#define __FRAME_STERO_G 480
#define __LIST_SIZE 512
/* ------------------begin:definition for uda1341---------------- */
#define UDA1341_ADDR 0x14
#define UDA1341_REG_DATA0 (UDA1341_ADDR + 0)
#define UDA1341_REG_STATUS (UDA1341_ADDR + 2)
/* status control */
#define STAT0 (0x00)
#define STAT0_RST (1 << 6)
#define STAT0_SC_MASK (3 << 4)
#define STAT0_SC_512FS (0 << 4)
#define STAT0_SC_384FS (1 << 4)
#define STAT0_SC_256FS (2 << 4)
#define STAT0_IF_MASK (7 << 1)
#define STAT0_IF_I2S (0 << 1)
#define STAT0_IF_LSB16 (1 << 1)
#define STAT0_IF_LSB18 (2 << 1)
#define STAT0_IF_LSB20 (3 << 1)
#define STAT0_IF_MSB (4 << 1)
#define STAT0_IF_LSB16MSB (5 << 1)
#define STAT0_IF_LSB18MSB (6 << 1)
#define STAT0_IF_LSB20MSB (7 << 1)
#define STAT0_DC_FILTER (1 << 0)
#define STAT0_DC_NO_FILTER (0 << 0)
#define STAT1 (0x80)
#define STAT1_DAC_GAIN (1 << 6)
#define STAT1_ADC_GAIN (1 << 5)
#define STAT1_ADC_POL (1 << 4)
#define STAT1_DAC_POL (1 << 3)
#define STAT1_DBL_SPD (1 << 2)
#define STAT1_ADC_ON (1 << 1)
#define STAT1_DAC_ON (1 << 0)
/* data0 direct control */
#define DATA0 (0x00)
#define DATA0_VOLUME_MASK (0x3f)
#define DATA0_VOLUME(x) (x)
#define DATA1 (0x40)
#define DATA1_BASS(x) ((x) << 2)
#define DATA1_BASS_MASK (15 << 2)
#define DATA1_TREBLE(x) (x)
#define DATA1_TREBLE_MASK (3)
#define DATA2 (0x80)
#define DATA2_PEAKAFTER (0x1 << 5)
#define DATA2_DEEMP_NONE (0x0 << 3)
#define DATA2_DEEMP_32KHz (0x1 << 3)
#define DATA2_DEEMP_44KHz (0x2 << 3)
#define DATA2_DEEMP_48KHz (0x3 << 3)
#define DATA2_MUTE (0x1 << 2)
#define DATA2_FILTER_FLAT (0x0 << 0)
#define DATA2_FILTER_MIN (0x1 << 0)
#define DATA2_FILTER_MAX (0x3 << 0)
/* data0 extend control */
#define EXTADDR(n) (0xc0 | (n))
#define EXTDATA(d) (0xe0 | (d))
#define EXT0 0
#define EXT0_CH1_GAIN(x) (x)
#define EXT1 1
#define EXT1_CH2_GAIN(x) (x)
#define EXT2 2
#define EXT2_MIC_GAIN_MASK (7 << 2)
#define EXT2_MIC_GAIN(x) ((x) << 2)
#define EXT2_MIXMODE_DOUBLEDIFF (0)
#define EXT2_MIXMODE_CH1 (1)
#define EXT2_MIXMODE_CH2 (2)
#define EXT2_MIXMODE_MIX (3)
#define EXT4 4
#define EXT4_AGC_ENABLE (1 << 4)
#define EXT4_INPUT_GAIN_MASK (3)
#define EXT4_INPUT_GAIN(x) ((x) & 3)
#define EXT5 5
#define EXT5_INPUT_GAIN_MASK (0x7f)
#define EXT5_INPUT_GAIN(x) ((x) >> 2)
#define EXT6 6
#define EXT6_AGC_CONSTANT_MASK (7 << 2)
#define EXT6_AGC_CONSTANT(x) ((x) << 2)
#define EXT6_AGC_LEVEL_MASK (3)
#define EXT6_AGC_LEVEL(x) (x)
/* ------------------end:definition for uda1341---------------- */
#define GPIO_L3CLOCK_NUM 9 /* gpioe 9 */
#define GPIO_L3DATA_NUM 8 /* gpioe 8 */
#define GPIO_L3MODE_NUM 7 /* gpioe 7 */
#define NOCACHEBASE 0x30100000
#define __writemem_G_ADR (NOCACHEBASE - __FRAME_STERO_G*2)
#define __readmem_G_ADR (__writemem_G_ADR - __FRAME_STERO_G*2)
#define __writemem_ADR (__readmem_G_ADR - __LIST_SIZE*4)
#define __readmem_ADR (__writemem_ADR - __LIST_SIZE*4)
#define __writemem_G (short *)(__writemem_G_ADR)
#define __readmem_G (short *)(__readmem_G_ADR)
#define __writemem (short *)(__writemem_ADR)
#define __readmem (short *)(__readmem_ADR) /* 0x300FE880 */
#endif
/*-----------------------------------------------------------------------------
SPI SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define SPI0_BASE 0x59000000 /* SPI channel 0 register base */
#define SPCON0 (*(volatile unsigned *)(SPI0_BASE + 0x00)) /* SPI channel 0 control register */
#define SPSTA0 (*(volatile unsigned *)(SPI0_BASE + 0x04)) /* SPI channel 0 status register */
#define SPPIN0 (*(volatile unsigned *)(SPI0_BASE + 0x08)) /* SPI channel 0 pin control register */
#define SPPRE0 (*(volatile unsigned *)(SPI0_BASE + 0x0c)) /* SPI cannel 0 baud rate prescaler register */
#define SPTDAT0 (*(volatile unsigned *)(SPI0_BASE + 0x10)) /* SPI channel 0 Tx data register */
#define SPRDAT0 (*(volatile unsigned *)(SPI0_BASE + 0x14)) /* SPI channel 0 Rx data register */
#define SPI1_BASE 0x59000020 /* SPI channel 1 register base */
#define SPCON1 (*(volatile unsigned *)(SPI1_BASE + 0x00)) /* SPI channel 1 control register */
#define SPSTA1 (*(volatile unsigned *)(SPI1_BASE + 0x04)) /* SPI channel 1 status register */
#define SPPIN1 (*(volatile unsigned *)(SPI1_BASE + 0x08)) /* SPI channel 1 pin control register */
#define SPPRE1 (*(volatile unsigned *)(SPI1_BASE + 0x0c)) /* SPI cannel 1 baud rate prescaler register */
#define SPTDAT1 (*(volatile unsigned *)(SPI1_BASE + 0x10)) /* SPI channel 1 Tx data register */
#define SPRDAT1 (*(volatile unsigned *)(SPI1_BASE + 0x14)) /* SPI channel 1 Rx data register */
/*-----------------------------------------------------------------------------
CAMERA INTERFACE SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define CAM_BASE 0x4F000000 /* CAMERA register base */
#define CISRCFMT (*(volatile unsigned *)(CAM_BASE + 0x00)) /* Input source format register */
#define CIWDOFST (*(volatile unsigned *)(CAM_BASE + 0x04)) /* Window offset register */
#define CIGCTRL (*(volatile unsigned *)(CAM_BASE + 0x08)) /* Global control register */
#define CICOYSA1 (*(volatile unsigned *)(CAM_BASE + 0x18)) /* Y 1st frame start address for codec DMA */
#define CICOYSA2 (*(volatile unsigned *)(CAM_BASE + 0x1C)) /* Y 2nd frame start address for codec DMA */
#define CICOYSA3 (*(volatile unsigned *)(CAM_BASE + 0x20)) /* Y 3nd frame start address for codec DMA */
#define CICOYSA4 (*(volatile unsigned *)(CAM_BASE + 0x24)) /* Y 4th frame start address for codec DMA */
#define CICOCBSA1 (*(volatile unsigned *)(CAM_BASE + 0x28)) /* Cb 1st frame start address for codec DMA */
#define CICOCBSA2 (*(volatile unsigned *)(CAM_BASE + 0x2C)) /* Cb 2nd frame start address for codec DMA */
#define CICOCBSA3 (*(volatile unsigned *)(CAM_BASE + 0x30)) /* Cb 3nd frame start address for codec DMA */
#define CICOCBSA4 (*(volatile unsigned *)(CAM_BASE + 0x34)) /* Cb 4th frame start address for codec DMA */
#define CICOCRSA1 (*(volatile unsigned *)(CAM_BASE + 0x38)) /* Cr 1st frame start address for codec DMA */
#define CICOCRSA2 (*(volatile unsigned *)(CAM_BASE + 0x3C)) /* Cr 2nd frame start address for codec DMA */
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