drv_defs.h

uCosII是一个小型的多任务调度内核

#define EP_INT_EN_REG    (*(volatile unsigned char *)(USBD_BASE + 0x15C))    /* Determine which interrupt is enabled */
#define USB_INT_EN_REG   (*(volatile unsigned char *)(USBD_BASE + 0x16C))    /* Determine which interrupt is enabled */
#define FRAME_NUM1_REG   (*(volatile unsigned char *)(USBD_BASE + 0x170))    /* Frame number lower byte register */
#define FRAME_NUM2_REG   (*(volatile unsigned char *)(USBD_BASE + 0x174))    /* Frame number higher byte register */
#define INDEX_REG        (*(volatile unsigned char *)(USBD_BASE + 0x178))    /* Register index register */
#define MAXP_REG         (*(volatile unsigned char *)(USBD_BASE + 0x180))    /* End Point MAX packet register */
#define EP0_CSR          (*(volatile unsigned char *)(USBD_BASE + 0x184))    /* Endpoint 0 status register */
#define IN_CSR1_REG      (*(volatile unsigned char *)(USBD_BASE + 0x184))    /* IN END POINT control status register1 */
#define IN_CSR2_REG      (*(volatile unsigned char *)(USBD_BASE + 0x188))    /* IN END POINT control status register2 */
#define OUT_CSR1_REG     (*(volatile unsigned char *)(USBD_BASE + 0x190))    /* End Point out control status register1 */
#define OUT_CSR2_REG     (*(volatile unsigned char *)(USBD_BASE + 0x194))    /* End Point out control status register2 */
#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)(USBD_BASE + 0x198))   /* End Point out write count register1 */
#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)(USBD_BASE + 0x19C))   /* End Point out write count register2 */
#define EP0_FIFO         (*(volatile unsigned char *)(USBD_BASE + 0x1C0))    /* End Point0 FIFO register */
#define EP1_FIFO         (*(volatile unsigned char *)(USBD_BASE + 0x1C4))    /* End Point1 FIFO register */
#define EP2_FIFO         (*(volatile unsigned char *)(USBD_BASE + 0x1C8))    /* End Point2 FIFO register */
#define EP3_FIFO         (*(volatile unsigned char *)(USBD_BASE + 0x1CC))    /* End Point3 FIFO register */
#define EP4_FIFO         (*(volatile unsigned char *)(USBD_BASE + 0x1D0))    /* End Point4 FIFO register */
#define EP1_DMA_CON      (*(volatile unsigned char *)(USBD_BASE + 0x200))    /* EP1 DMA interface control register */
#define EP2_DMA_CON      (*(volatile unsigned char *)(USBD_BASE + 0x218))    /* EP2 DMA interface control register */
#define EP3_DMA_CON      (*(volatile unsigned char *)(USBD_BASE + 0x240))    /* EP3 DMA interface control register */
#define EP4_DMA_CON      (*(volatile unsigned char *)(USBD_BASE + 0x258))    /* EP4 DMA interface control register */
#define EP1_DMA_UNIT     (*(volatile unsigned char *)(USBD_BASE + 0x204))    /* EP1 DMA transfer unit counter base register */
#define EP2_DMA_UNIT     (*(volatile unsigned char *)(USBD_BASE + 0x21C))    /* EP2 DMA transfer unit counter base register */
#define EP3_DMA_UNIT     (*(volatile unsigned char *)(USBD_BASE + 0x244))    /* EP3 DMA transfer unit counter base register */
#define EP4_DMA_UNIT     (*(volatile unsigned char *)(USBD_BASE + 0x25C))    /* EP4 DMA transfer unit counter base register */
#define EP1_DMA_FIFO     (*(volatile unsigned char *)(USBD_BASE + 0x208))    /* EP1 DMA transfer FIFO counter base register */
#define EP2_DMA_FIFO     (*(volatile unsigned char *)(USBD_BASE + 0x220))    /* EP2 DMA transfer FIFO counter base register */
#define EP3_DMA_FIFO     (*(volatile unsigned char *)(USBD_BASE + 0x248))    /* EP3 DMA transfer FIFO counter base register */
#define EP4_DMA_FIFO     (*(volatile unsigned char *)(USBD_BASE + 0x260))    /* EP4 DMA transfer FIFO counter base register */
#define EP1_DMA_TTC_L    (*(volatile unsigned char *)(USBD_BASE + 0x20C))    /* EP1 DMA total transfer counter(lower byte) */
#define EP1_DMA_TTC_M    (*(volatile unsigned char *)(USBD_BASE + 0x210))    /* EP1 DMA total transfer counter(middle byte) */
#define EP1_DMA_TTC_H    (*(volatile unsigned char *)(USBD_BASE + 0x214))    /* EP1 DMA total transfer counter(higher byte) */
#define EP2_DMA_TTC_L    (*(volatile unsigned char *)(USBD_BASE + 0x224))    /* EP2 DMA total transfer counter(lower byte) */
#define EP2_DMA_TTC_M    (*(volatile unsigned char *)(USBD_BASE + 0x228))    /* EP2 DMA total transfer counter(middle byte) */
#define EP2_DMA_TTC_H    (*(volatile unsigned char *)(USBD_BASE + 0x22C))    /* EP2 DMA total transfer counter(higher byte) */
#define EP3_DMA_TTC_L    (*(volatile unsigned char *)(USBD_BASE + 0x24C))    /* EP3 DMA total transfer counter(lower byte) */
#define EP3_DMA_TTC_M    (*(volatile unsigned char *)(USBD_BASE + 0x250))    /* EP3 DMA total transfer counter(middle byte) */
#define EP3_DMA_TTC_H    (*(volatile unsigned char *)(USBD_BASE + 0x254))    /* EP3 DMA total transfer counter(higher byte) */
#define EP4_DMA_TTC_L    (*(volatile unsigned char *)(USBD_BASE + 0x264))    /* EP4 DMA total transfer counter(lower byte) */
#define EP4_DMA_TTC_M    (*(volatile unsigned char *)(USBD_BASE + 0x268))    /* EP4 DMA total transfer counter(middle byte) */
#define EP4_DMA_TTC_H    (*(volatile unsigned char *)(USBD_BASE + 0x26C))    /* EP4 DMA total transfer counter(higher byte) */



/*-----------------------------------------------------------------------------
@_@                 INTERRUPT CONTROLLER SPECIAL REGISTERS and vector
------------------------------------------------------------------------------*/
#define INT_BASE    0x4A000000                                 
#define	SRCPND      (*(volatile unsigned *)INT_BASE)          /* Indicate the interrupt request status */
#define	INTMOD      (*(volatile unsigned *)(INT_BASE + 0x04)) /* Interrupt mode regiseter */
#define	INTMSK      (*(volatile unsigned *)(INT_BASE + 0x08)) /* INTERRUPT MASK (INTMSK) REGISTER */
#define	PRIORITY    (*(volatile unsigned *)(INT_BASE + 0x0c)) /* IRQ priority control register */
#define	INTPND      (*(volatile unsigned *)(INT_BASE + 0x10)) /* Indicate the interrupt request status. */
#define	INTOFFSET   (*(volatile unsigned *)(INT_BASE + 0x14)) /* Indicate the IRQ interrupt request source */
#define	SUBSRCPND   (*(volatile unsigned *)(INT_BASE + 0x18)) /* Indicate the interrupt request status */
#define	INTSUBMSK   (*(volatile unsigned *)(INT_BASE + 0x1c)) /* INTERRUPT SUB MASK (INTSUBMSK) REGISTER */
/* vector define */
#define IRQ_VECTOR_EINT0             0
#define IRQ_VECTOR_EINT1             1
#define IRQ_VECTOR_EINT2             2
#define IRQ_VECTOR_EINT3             3
#define IRQ_VECTOR_EINT4_7           4
#define IRQ_VECTOR_EINT8_23          5
#define IRQ_VECTOR_6                 6
#define IRQ_VECTOR_BATT_FLT          7
#define IRQ_VECTOR_TICK              8
#define IRQ_VECTOR_WDT               9
#define IRQ_VECTOR_TIMER0           10
#define IRQ_VECTOR_TIMER1           11
#define IRQ_VECTOR_TIMER2           12
#define IRQ_VECTOR_TIMER3           13
#define IRQ_VECTOR_TIMER4           14
#define IRQ_VECTOR_UART2            15
#define IRQ_VECTOR_LCD              16
#define IRQ_VECTOR_DMA0             17
#define IRQ_VECTOR_DMA1             18
#define IRQ_VECTOR_DMA2             19
#define IRQ_VECTOR_DMA3             20
#define IRQ_VECTOR_SDI              21
#define IRQ_VECTOR_SPI0             22
#define IRQ_VECTOR_UART1            23
#define IRQ_VECTOR_24               24
#define IRQ_VECTOR_USBD             25
#define IRQ_VECTOR_USBH             26
#define IRQ_VECTOR_IIC              27
#define IRQ_VECTOR_UART0            28
#define IRQ_VECTOR_SPI1             29
#define IRQ_VECTOR_RTC              30
#define IRQ_VECTOR_ADC              31
/* INTSUBMASK define */        
#define INT_RXD0    0
#define INT_TXD0    1
#define INT_ERR0    2
#define INT_RXD1    3
#define INT_TXD1    4
#define INT_ERR1    5
#define INT_RXD2    6
#define INT_TXD2    7
#define INT_ERR2    8
#define INT_TC      9
#define INT_ADC	    10
        
        
/*-----------------------------------------------------------------------------
@_@                LCD CONTROLLER SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define LCD_BASE    0x4D000000
#define	LCDCON1     (*(volatile unsigned *)LCD_BASE)          /* LCD Control 1 Register */
#define	LCDCON2     (*(volatile unsigned *)(LCD_BASE + 0x04)) /* LCD Control 2 Register */
#define	LCDCON3     (*(volatile unsigned *)(LCD_BASE + 0x08)) /* LCD Control 3 Register */
#define	LCDCON4     (*(volatile unsigned *)(LCD_BASE + 0x0c)) /* LCD Control 4 Register */
#define	LCDCON5     (*(volatile unsigned *)(LCD_BASE + 0x10)) /* LCD Control 5 Register */
#define	LCDSADDR1   (*(volatile unsigned *)(LCD_BASE + 0x14)) /* FRAME BUFFER START ADDRESS 1 REGISTER */
#define	LCDSADDR2   (*(volatile unsigned *)(LCD_BASE + 0x18)) /* FRAME Buffer Start Address 2 Register */
#define	LCDSADDR3   (*(volatile unsigned *)(LCD_BASE + 0x1c)) /* FRAME Buffer Start Address 3 Register */
#define	REDLUT      (*(volatile unsigned *)(LCD_BASE + 0x20)) /* RED Lookup Table Register */
#define	GREENLUT    (*(volatile unsigned *)(LCD_BASE + 0x24)) /* GREEN Lookup Table Register */
#define	BLUELUT     (*(volatile unsigned *)(LCD_BASE + 0x28)) /* BLUE Lookup Table Register */
#define	DITHMODE    (*(volatile unsigned *)(LCD_BASE + 0x4c)) /* Dithering Mode Register */
#define	TPAL        (*(volatile unsigned *)(LCD_BASE + 0x50)) /* Temp Palette Register */
#define	LCDINTPND   (*(volatile unsigned *)(LCD_BASE + 0x54)) /* LCD Interrupt Pending Register */
#define	LCDSRCPND   (*(volatile unsigned *)(LCD_BASE + 0x58)) /* LCD Source Pending Register */
#define	LCDINTMSK   (*(volatile unsigned *)(LCD_BASE + 0x5c)) /* LCD Interrupt Mask Register */
#define	LPCSEL     (*(volatile unsigned *)(LCD_BASE + 0x60)) /* TCON Control Register */



/*-----------------------------------------------------------------------------
                    REAL TIME CLOCK SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define RTC_BASE    0x57000000
#define	RTCCON      (*(volatile unsigned char *)(RTC_BASE + 0x40)) /* RTC control register */
#define	TICNT       (*(volatile unsigned char *)(RTC_BASE + 0x44)) /* Tick time count register */
#define	RTCALM      (*(volatile unsigned char *)(RTC_BASE + 0x50)) /* RTC alarm control register */
#define	ALMSEC      (*(volatile unsigned char *)(RTC_BASE + 0x54)) /* Alarm second data register */
#define	ALMMIN      (*(volatile unsigned char *)(RTC_BASE + 0x58)) /* Alarm minute data register */
#define	ALMHOUR     (*(volatile unsigned char *)(RTC_BASE + 0x5C)) /* Alarm hour data register */
#define	ALMDATE     (*(volatile unsigned char *)(RTC_BASE + 0x60)) /* Alarm date data register */
#define	ALMMON      (*(volatile unsigned char *)(RTC_BASE + 0x64)) /* Alarm month data register */
#define	ALMYEAR     (*(volatile unsigned char *)(RTC_BASE + 0x68)) /* Alarm year data register */
#define	BCDSEC      (*(volatile unsigned char *)(RTC_BASE + 0x70)) /* BCD second register */
#define	BCDMIN      (*(volatile unsigned char *)(RTC_BASE + 0x74)) /* BCD minute register */
#define	BCDHOUR     (*(volatile unsigned char *)(RTC_BASE + 0x78)) /* BCD hour register */
#define	BCDDATE     (*(volatile unsigned char *)(RTC_BASE + 0x7C)) /* BCD date register */
#define	BCDDAY      (*(volatile unsigned char *)(RTC_BASE + 0x80)) /* BCD a day of the week register */
#define	BCDMON      (*(volatile unsigned char *)(RTC_BASE + 0x84)) /* BCD month register */
#define	BCDYEAR     (*(volatile unsigned char *)(RTC_BASE + 0x88)) /* BCD year register */

/* date time data struct, use BCD code */
typedef struct DATE_TIME {
	unsigned char second;        /* second */
	unsigned char minute;        /* minute */
	unsigned char hour;          /* hour   */
	unsigned char day;           /* day    */
	unsigned char week;          /* week   */
	unsigned char month;         /* month  */
	unsigned char year;          /* year   */
} TDATE_TIME, *pDATE_TIME;

/* RTC value type */
typedef enum RTC_TYPE 
{
	RTC_SECOND = 2,	   
	RTC_MINUTE,
	RTC_HOUR,
	RTC_DAY,
	RTC_WEEK,
	RTC_MONTH,
	RTC_YEAR
} TRTC_TYPE;


/*-----------------------------------------------------------------------------
                    WATCHDOG TIMER SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define WTD_BASE    0x53000000
#define	WTCON       (*(volatile unsigned *)WTD_BASE)              /* Watchdog timer control register */
#define	WTDAT       (*(volatile unsigned *)(WTD_BASE + 0x04))     /* Watchdog timer data register */
#define	WTCNT       (*(volatile unsigned *)(WTD_BASE + 0x08))     /* Watchdog timer count register */


/*-----------------------------------------------------------------------------
                   IIC-BUS INTERFACE SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define IIC_BASE    0x54000000
#define IICCON      (*(volatile unsigned *)(IIC_BASE + 0x00))     /* IIC-Bus control register */
#define IICSTAT     (*(volatile unsigned *)(IIC_BASE + 0x04))     /* IIC-Bus control/status register */
#define IICADD      (*(volatile unsigned *)(IIC_BASE + 0x08))     /* IIC-Bus address register */
#define IICDS       (*(volatile unsigned *)(IIC_BASE + 0x0c))     /* IIC-Bus transmit/receive data shift register */
#define IICLC       (*(volatile unsigned *)(IIC_BASE + 0x10))     /* IIC-Bus multi-master line control register */

/*-----------------------------------------------------------------------------
                   AC97 INTERFACE SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define AC97_BASE    0x5B000000
#define AC_GLBCTRL   (*(volatile unsigned *)(AC97_BASE + 0x00))     /* AC97 global control register */
#define AC_GLBSTAT   (*(volatile unsigned *)(AC97_BASE + 0x04))     /* AC97 global status register */
#define AC_CODEC_CMD (*(volatile unsigned *)(AC97_BASE + 0x08))     /* AC97 codec command register */
#define AC_CODEC_STAT (*(volatile unsigned *)(AC97_BASE + 0x0C))    /* AC97 codec status register */
#define AC_PCMADDR   (*(volatile unsigned *)(AC97_BASE + 0x10))     /* AC97 pcm out/in fifo address register */
#define AC_MICADDR   (*(volatile unsigned *)(AC97_BASE + 0x14))     /* AC97 mic out/in fifo address register */
#define AC_PCMDATA   (*(volatile unsigned *)(AC97_BASE + 0x18))     /* AC97 pcm out/in fifo data register */
#define AC_MICDATA   (*(volatile unsigned *)(AC97_BASE + 0x1C))     /* AC97 mic out/in fifo data register */

#if 0
/* ywj 060930*/
typedef enum __AUDIO_STATUS
{
	AUDIO_NONE,
	AUDIO_PLAYING,
	AUDIO_RECORDING
}AUDIO_STATUS;

typedef enum __RECORD_MIC
{
	RECORD_NONE,
	RECORD_MIC_HS,
	RECORD_MIC_HF
}RECORD_MIC;


typedef enum __PLAY_SPEAKER
{
	PLAY_NONE,
	PLAY_SPK_HS,
	PLAY_SPK_HF
}PLAY_SPEAKER;
#endif

/*-----------------------------------------------------------------------------
                   IIS-BUS INTERFACE SPECIAL REGISTERS
------------------------------------------------------------------------------*/
#define IIS_BASE    0x55000000
#define IISCON      (*(volatile unsigned *)(IIS_BASE + 0x00))     /* IIS control register */
#define IISMOD      (*(volatile unsigned *)(IIS_BASE + 0x04))     /* IIS mode register */
#define IISPSR      (*(volatile unsigned *)(IIS_BASE + 0x08))     /* IIS prescaler register */
#define IISFCON     (*(volatile unsigned *)(IIS_BASE + 0x0c))     /* IIS FIFO interface register */
#define IISFIFO     (*(volatile short *)(IIS_BASE + 0x10))     /* IIS FIFO register */

#define IISCON_CH_RIGHT (1 << 8)        /* Right channel */