os_cpu_a.asm

uCosII是一个小型的多任务调度内核

	MOV r0, lr
	B OS_CPU_ARM_ExceptResetHndlr


;********************************************************************************************************
;                                UNDEFINED INSTRUCTION EXCEPTION HANDLER
;
; Register Usage:  R0     Exception Type
;                  R1
;                  R2
;                  R3     Return PC
;********************************************************************************************************

;    AREA CODE, CODE, READONLY
;    CODE32

OS_CPU_ARM_ExceptUndefInstrHndlr

	MOV r0, lr
	B OS_CPU_ARM_ExceptUndefInstrHndlr

;********************************************************************************************************
;                                 SOFTWARE INTERRUPT EXCEPTION HANDLER
;
; Register Usage:  R0     Exception Type
;                  R1
;                  R2
;                  R3     Return PC
;********************************************************************************************************

;    AREA CODE, CODE, READONLY
;    CODE32

OS_CPU_ARM_ExceptSwiHndlr

	MOV r0, lr
	B OS_CPU_ARM_ExceptSwiHndlr


;********************************************************************************************************
;                                   PREFETCH ABORT EXCEPTION HANDLER
;
; Register Usage:  R0     Exception Type
;                  R1
;                  R2
;                  R3     Return PC
;********************************************************************************************************

;    AREA CODE, CODE, READONLY
;    CODE32

OS_CPU_ARM_ExceptPrefetchAbortHndlr

	MOV r0, lr
	B OS_CPU_ARM_ExceptPrefetchAbortHndlr


;********************************************************************************************************
;                                     DATA ABORT EXCEPTION HANDLER
;
; Register Usage:  R0     Exception Type
;                  R1
;                  R2
;                  R3     Return PC
;********************************************************************************************************

;    AREA CODE, CODE, READONLY
;    CODE32

OS_CPU_ARM_ExceptDataAbortHndlr

	MOV r0, lr
	B OS_CPU_ARM_ExceptDataAbortHndlr


;********************************************************************************************************
;                                    ADDRESS ABORT EXCEPTION HANDLER
;
; Register Usage:  R0     Exception Type
;                  R1
;                  R2
;                  R3     Return PC
;********************************************************************************************************

;    AREA CODE, CODE, READONLY
;    CODE32

OS_CPU_ARM_ExceptAddrAbortHndlr

	MOV r0, lr
	B OS_CPU_ARM_ExceptAddrAbortHndlr


;********************************************************************************************************
;                               FAST INTERRUPT REQUEST EXCEPTION HANDLER
;
; Register Usage:  R0     Exception Type
;                  R1
;                  R2
;                  R3     Return PC
;********************************************************************************************************

;    AREA CODE, CODE, READONLY
;    CODE32

OS_CPU_ARM_ExceptFiqHndlr

	MOV r0, lr
	B OS_CPU_ARM_ExceptFiqHndlr



;********************************************************************************************************
;                                  INTERRUPT REQUEST EXCEPTION HANDLER
;
; Register Usage:  R0     Exception Type
;                  R1
;                  R2
;                  R3     Return PC
;********************************************************************************************************

OS_CPU_ARM_IRQ
    SUB     LR, LR, #4                                          ; LR offset to return from this exception: -4.
    STMFD   SP!, {R0-R12, LR}                                   ; Push working registers.
    MOV     R3, LR                                              ; Save link register.

    LDR     r4, =0x4A000000                 ; load Interrupt Control Base
    LDR     r0, [r4,#8]                     ; Get mask register value
    STMDB   sp!,{r0}                        ; Put the mask register value on the IRQ stack

	MVN     r0, #0                      
	STR     r0, [r4,#8]                      ; Mask all interrupts, NOT allow interrupt nest


    MRS     R1, SPSR                                            ; Save CPSR (i.e. exception's SPSR).
                                                                ; DETERMINE IF WE INTERRUPTED A TASK OR ANOTHER LOWER PRIORITY EXCEPTION:
                                                                ;   SPSR.Mode = SVC                :  task,
                                                                ;   SPSR.Mode = FIQ, IRQ, ABT, UND :  other exceptions,
                                                                ;   SPSR.Mode = USR                : *unsupported state*.

    MRS     R2, CPSR                                            ; Save exception's CPSR.
    ADD     R4, SP, #4                                          ; Save exception's stack pointer.

                                                                ; Change to SVC mode & disable interruptions.
    MSR     CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)

                                                                ; SAVE TASK'S CONTEXT ONTO TASK'S STACK:
    STMFD   SP!, {R3}                                           ;   Push task's PC,
    STMFD   SP!, {LR}                                           ;   Push task's LR,
    STMFD   SP!, {R5-R12}                                       ;   Push task's R12-R5,
    LDMFD   R4!, {R5-R9}                                        ;   Move task's R4-R0 from exception stack to task's stack.
    STMFD   SP!, {R5-R9}
    STMFD   SP!, {R1}                                           ;   Push task's CPSR (i.e. exception SPSR).

                                                                ; if (OSRunning == 1)
    LDR     R1, __OS_Running
    LDRB    R1, [R1]
    CMP     R1, #1
    BNE     OS_CPU_ARM_ExceptHndlr_Exit

                                                                ; HANDLE NESTING COUNTER:
    LDR     R3, __OS_IntNesting                                 ;   OSIntNesting++;
    LDRB    R4, [R3]
    ADD     R4, R4, #1
    STRB    R4, [R3]

    LDR     R3, __OS_TCBCur                                     ;   OSTCBCur->OSTCBStkPtr = SP;
    LDR     R4, [R3]
    STR     SP, [R4]

    LDR     r4, =0x4A000000                 ; load Interrupt Control Base
    LDR     r0, [r4,#0x14]                   ; Read the Pending reg number
	MOV     r1, #1                           ; Build mask
	MOV     r1, r1, LSL r0                   ; Use vector number to set mask to correct bit position
	STR     r1, [r4, #0]                     ; clear SOURCE PENDING interrupt
	STR     r1, [r4, #0x10]                  ; clear PENDING interrupt

    LDR     r4, IRQ_Vectors                 ; Get IRQ vector table address
    MOV     r3, r0, LSL #2                  ; Multiply vector by 4 to get offset into table
    ADD     r4, r4, r3                      ; Adjust vector table address to correct offset
    LDR     r3, [r4,#0]                     ; Load branch address from vector table

    STMFD   sp!, {r2}                                           ;   Push task's LR,
    MOV     LR, PC
    BX      R3
    LDMFD   sp!, {r2}                        

OS_CPU_ARM_ExceptHndlr_Exit
    MSR     CPSR_cxsf, R2                                       ; RESTORE INTERRUPTED MODE.

    LDMFD   SP!, {R1}                        
    LDR     r0, =0x4A000000                 ; load Interrupt Control Base
    STR     r1, [r0,#8]                     ; Restore mask register value

    ADD     SP, SP, #(14 * 4)               ; Adjust stack pointer
                                                                ; Change to SVC mode & disable interruptions.
    MSR     CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)

                                                                ; Call OSIntExit().  This call MAY never return if a ready
                                                                ;  task with higher priority than the interrupted one is
                                                                ;  found.
    LDR     R0, __OS_IntExit
    MOV     LR, PC
    BX      R0

                                                                ; RESTORE NEW TASK'S CONTEXT:
    LDMFD   SP!, {R0}                                           ;    Pop new task's CPSR,
    MSR     SPSR_cxsf, R0

    LDMFD   SP!, {R0-R12, LR, PC}^                              ;    Pop new task's context.

;************************************
;* End Specific Code added by wyf
;************************************


;*********************************************************************************************************
;                                     POINTERS TO VARIABLES
;*********************************************************************************************************

;    AREA CODE, CODE, READONLY
;    CODE32

__OS_Running
    DCD     OSRunning

__OS_PrioCur
    DCD     OSPrioCur

__OS_PrioHighRdy
    DCD     OSPrioHighRdy

__OS_TCBCur
    DCD     OSTCBCur

__OS_TCBHighRdy
    DCD     OSTCBHighRdy

__OS_IntNesting
    DCD     OSIntNesting

__OS_TaskSwHook
    DCD     OSTaskSwHook

__OS_IntExit
    DCD     OSIntExit

__OS_CPU_ExceptHndlr
    DCD     OS_CPU_ExceptHndlr


    END