📄 os_cpu_a.asm
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;
;********************************************************************************************************
; uC/OS-II
; The Real-Time Kernel
;
;
; (c) Copyright 1992-2007, Micrium, Weston, FL
; All Rights Reserved
;
; Generic ARM Port
;
; File : OS_CPU_A.ASM
; Version : V1.82
; By : Jean J. Labrosse
; Jean-Denis Hatier
;
; For : ARM7 or ARM9
; Mode : ARM or Thumb
; Toolchain : RealView Development Suite
; RealView Microcontroller Development Kit (MDK)
; ARM Developer Suite (ADS)
; Keil uVision
;********************************************************************************************************
;
;********************************************************************************************************
; PUBLIC FUNCTIONS
;********************************************************************************************************
; External references.
IMPORT OSRunning
IMPORT OSPrioCur
IMPORT OSPrioHighRdy
IMPORT OSTCBCur
IMPORT OSTCBHighRdy
IMPORT OSIntNesting
IMPORT OSIntExit
IMPORT OSTaskSwHook
IMPORT OSTimeTick
IMPORT OS_Dispatch_LISR
IMPORT OS_CInitialize
IMPORT INT_System_Stk_Limit
IMPORT INT_System_Stack_SP
IMPORT INT_IRQ_Stack_SP
IMPORT INT_FIQ_Stack_SP
IMPORT INT_First_Avail_Mem
; Functions declared in this file.
EXPORT OS_CPU_SR_Save
EXPORT OS_CPU_SR_Restore
EXPORT OSStartHighRdy
EXPORT OSCtxSw
EXPORT OSIntCtxSw
; Functions related to exception handling.
EXPORT OS_CPU_ARM_ExceptResetHndlr
EXPORT OS_CPU_ARM_ExceptUndefInstrHndlr
EXPORT OS_CPU_ARM_ExceptSwiHndlr
EXPORT OS_CPU_ARM_ExceptPrefetchAbortHndlr
EXPORT OS_CPU_ARM_ExceptDataAbortHndlr
EXPORT OS_CPU_ARM_ExceptAddrAbortHndlr
EXPORT OS_CPU_ARM_ExceptFiqHndlr
IMPORT OS_CPU_ExceptHndlr
;********************************************************************************************************
; EQUATES
;********************************************************************************************************
OS_CPU_ARM_CONTROL_INT_DIS EQU 0xC0 ; Disable both FIQ and IRQ.
OS_CPU_ARM_CONTROL_FIQ_DIS EQU 0x40 ; Disable FIQ.
OS_CPU_ARM_CONTROL_IRQ_DIS EQU 0x80 ; Disable IRQ.
OS_CPU_ARM_CONTROL_THUMB EQU 0x20 ; Set THUMB mode.
OS_CPU_ARM_CONTROL_ARM EQU 0x00 ; Set ARM mode.
OS_CPU_ARM_MODE_MASK EQU 0x1F
OS_CPU_ARM_MODE_USR EQU 0x10
OS_CPU_ARM_MODE_FIQ EQU 0x11
OS_CPU_ARM_MODE_IRQ EQU 0x12
OS_CPU_ARM_MODE_SVC EQU 0x13
OS_CPU_ARM_MODE_ABT EQU 0x17
OS_CPU_ARM_MODE_UND EQU 0x1B
OS_CPU_ARM_MODE_SYS EQU 0x1F
OS_CPU_ARM_EXCEPT_RESET EQU 0x00
OS_CPU_ARM_EXCEPT_UNDEF_INSTR EQU 0x01
OS_CPU_ARM_EXCEPT_SWI EQU 0x02
OS_CPU_ARM_EXCEPT_PREFETCH_ABORT EQU 0x03
OS_CPU_ARM_EXCEPT_DATA_ABORT EQU 0x04
OS_CPU_ARM_EXCEPT_ADDR_ABORT EQU 0x05
OS_CPU_ARM_EXCEPT_IRQ EQU 0x06
OS_CPU_ARM_EXCEPT_FIQ EQU 0x07
;********************************************************************************************************
; CODE GENERATION DIRECTIVES
;********************************************************************************************************
REQUIRE8
PRESERVE8
AREA CODE, CODE, READONLY
CODE32
INT_Vectors
LDR pc, INT_Initialize_Addr ; Reset
LDR pc, INT_Undef_Inst_Addr ; Undefined Instruction
LDR pc, INT_Software_Addr ; Software Generated
LDR pc, INT_Prefetch_Abort_Addr ; Prefetch Abort
LDR pc, INT_Data_Abort_Addr ; Data Abort
LDR pc, INT_Reserved_Addr ; Reserved
LDR pc, INT_IRQ_Addr ; Standard External Interrupt
LDR pc, INT_FIQ_Addr ; Fast External Interrupt
INT_Initialize_Addr DCD OS_Initialize
INT_Undef_Inst_Addr DCD OS_CPU_ARM_ExceptUndefInstrHndlr
INT_Software_Addr DCD OS_CPU_ARM_ExceptSwiHndlr
INT_Prefetch_Abort_Addr DCD OS_CPU_ARM_ExceptPrefetchAbortHndlr
INT_Data_Abort_Addr DCD OS_CPU_ARM_ExceptDataAbortHndlr
INT_Reserved_Addr DCD OS_CPU_ARM_ExceptAddrAbortHndlr
INT_IRQ_Addr DCD OS_CPU_ARM_IRQ
INT_FIQ_Addr DCD OS_CPU_ARM_ExceptFiqHndlr
INT_Vectors_Addr DCD INT_Vectors
System_Stk_Limit DCD INT_System_Stk_Limit
System_Stack_SP DCD INT_System_Stack_SP
IRQ_Stack_SP DCD INT_IRQ_Stack_SP
FIQ_Stack_SP DCD INT_FIQ_Stack_SP
First_Avail_Mem DCD INT_First_Avail_Mem
IRQ_Vectors DCD INT_IRQ_Vectors
INT_ADDR DCD 0xffff0000
INT_IRQ_Vectors
DCD OS_Dispatch_LISR ; Vector 0
DCD OS_Dispatch_LISR ; Vector 1
DCD OS_Dispatch_LISR ; Vector 2
DCD OS_Dispatch_LISR ; Vector 3
DCD OS_Dispatch_LISR ; Vector 4
DCD OS_Dispatch_LISR ; Vector 5
DCD OS_Dispatch_LISR ; Vector 6
DCD OS_Dispatch_LISR ; Vector 7
DCD OS_Dispatch_LISR ; Vector 8
DCD OS_Dispatch_LISR ; Vector 9
DCD OS_Dispatch_LISR ; Vector 10
DCD OSTimeTick ; Vector 11
DCD OS_Dispatch_LISR ; Vector 12
DCD OS_Dispatch_LISR ; Vector 13
DCD OS_Dispatch_LISR ; Vector 14
DCD OS_Dispatch_LISR ; Vector 15
DCD OS_Dispatch_LISR ; Vector 16
DCD OS_Dispatch_LISR ; Vector 17
DCD OS_Dispatch_LISR ; Vector 18
DCD OS_Dispatch_LISR ; Vector 19
DCD OS_Dispatch_LISR ; Vector 20
DCD OS_Dispatch_LISR ; Vector 21
DCD OS_Dispatch_LISR ; Vector 22
DCD OS_Dispatch_LISR ; Vector 23
DCD OS_Dispatch_LISR ; Vector 24
DCD OS_Dispatch_LISR ; Vector 25
DCD OS_Dispatch_LISR ; Vector 26
DCD OS_Dispatch_LISR ; Vector 27
DCD OS_Dispatch_LISR ; Vector 28
DCD OS_Dispatch_LISR ; Vector 29
DCD OS_Dispatch_LISR ; Vector 30
DCD OS_Dispatch_LISR ; Vector 31
;********************************************************************************************************
; void OS_Initialize(void)
;********************************************************************************************************
EXPORT OS_Initialize
OS_Initialize
; Insure that the processor is in supervisor mode.
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)
; IMPORT Cache_Init
; BL Cache_Init
; LDR r10,System_Stk_Limit ; Pickup the system stack limit (bottom of system stack)
; LDR r3,System_Limit ; Pickup sys stack limit addr
; STR r10,[r3, #0] ; Save stack limit
LDR sp,System_Stack_SP ; Set-up the system stack pointer
; LDR r3,System_Stack ; Pickup system stack address
; STR sp,[r3, #0] ; Save stack pointer
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_IRQ) ; Set the IRQ mode
LDR sp,IRQ_Stack_SP ; Setup IRQ stack pointer
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_FIQ) ; Set the FIQ mode
LDR sp,FIQ_Stack_SP ; Setup FIQ stack pointer
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC) ; return to supervisor mode
BL OS_Install_Vector_Table ; Install the vector table
BL OS_Timer_Initialize ; Initialize the timer
LDR r0,First_Avail_Mem ; Get address of first available memory
B OS_CInitialize ; to high-level initialization
;*********************************************************************************************************
; VOID OS_Install_Vector_Table(VOID)
;*********************************************************************************************************
OS_Install_Vector_Table
STMDB sp!,{r0-r9}
;*****************************
;* Begin Board Specific Code *
;*****************************
; --- disable all interrupt
LDR r0, =0x4A000008 ;INTERRUPT MASK REGISTER
LDR r1, =0xFFFFFFFF ;mask all interrupt
STR r1, [r0] ;save to register
; Install the vector table
LDR r8,INT_ADDR
LDR r9,INT_Vectors_Addr
LDMIA r9!,{r0-r7}
STMIA r8!,{r0-r7}
LDMIA r9!,{r0-r7}
STMIA r8!,{r0-r7}
;*****************************
;* End Board Specific Code *
;*****************************
LDMIA sp!,{r0-r9} ; Restore registers
BX lr ; Return to caller
;}
; End INT_Install_Vector_Table
;************************************************************************
;*
;* FUNCTION
;*
;* OS_Timer_Initialize
;*
;* DESCRIPTION
;*
;* This routine initializes the timer
;*
;* CALLED BY
;*
;* INT_Initialize
;*
;* CALLS
;*
;* None
;*
;* INPUTS
;*
;* None
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