926-ej.s

基于Freescale的MX21处理器的bootloader程序

;************************************************************************
;*  Name: 926-EJ.s
;*  Description: MC9328MX21 initialize routine
;*  Author: wyf
;*  Date: 2006.07.17
;************************************************************************
;************************************************************************
	PRESERVE8
	AREA cache926ej, CODE, READONLY
	INCLUDE MX21_defs.s

ttb_cache_on      EQU     1

ttb_first_level   EQU     0xc0000000 ; base address for level 1 translation table
ttb_second_level  EQU     0xc0004000

	ENTRY
	EXPORT Cache_Init
Cache_Init
;**********************************
;* Disable Cache                  * 
;**********************************
	MRC p15,0,r0,c1,c0,0
	LDR r1,=0x00001005 
	BIC r0,r0,r1 
	MCR p15,0,r0,c1,c0,0 
;************************************
;* Domain : 0(default)              *
;* SDRAM  : RW                      * 
;************************************
	LDR r0,=ttb_first_level         ; set start of Translation Table base (16k Boundary)
	MCR p15, 0, r0, c2, c0, 0       ; write to CP15 register 2

	LDR r1,=0xfff                   ; loop counter
	MOV r2,   #2_110000000000       ; set access permissions (AP) for full access SVC/USR (11:10)
	ORR r2,r2,#2_000000000000       ; set for domain 0 (8:5)
	ORR r2,r2,#2_000000010000       ; must be 1 (4)
	ORR r2,r2,#2_000000000000       ; set non cachable non bufferable (CB) (3:2)
	ORR r2,r2,#2_000000000010       ; set for 1Mb section (1:0)
1
	ORR r3,r2,r1,lsl#20             ; use loop counter to create individual table entries
	STR r3,[r0,r1,lsl#2]            ; str r3 at TTB base + loopcount*4
	SUBS r1,r1,#1                   ; decrement loop counter
	BPL %B1
	
;************************************
;* Domain : 1                       *
;* SDRAM  : RW & Cached & Buffered  * 
;* Base   : 0xc0800000              *
;* Len    : 0x03800000              *
;************************************
	LDR r1,=ttb_first_level
	LDR r2,=0xc0800000
	ADD r1,r2,LSR #18               ; Calculte offset

	IF ttb_cache_on = 1
	LDR r3,=0xc3e                   ; Domain 1, enable Cache
	ELSE
	LDR r3,=0xc32                   ; Domain 1, disable Cache
	ENDIF

	ADD r3,r2,r3
	LDR r0,=56                      ; Total 56MB
2
	STR r3,[r1],#4
	ADD r3,r3,#0x100000
	SUBS r0,r0,#1
	BNE %B2

;************************************
;* Domain : 2                       *
;* VRAM   : RW & Cached & Buffered  * 
;* Base   :  section 0x00000000     *
;*           VRAM    0xfffff000     *
;*              ---->0x00000000     *     
;* Len    : 0x1000                  *
;************************************
	LDR r1,=ttb_first_level
;	LDR r2,=0xfff00000
	LDR r2,=0x00000000
	ADD r1,r2,LSR #18               ; Calculte offset
	LDR r2,=ttb_second_level        ; Level2 base
	LDR r3,=0x51                    ; Domain 2, coarse page table(4K)
	ADD r3,r2,r3
	STR r3,[r1]
;	LDR r1,=0xf0000              ; Virtual Memory
	LDR r1,=0x0000               ; Virtual Memory
	ADD r2,r1,LSR #10               ; Calculate small page offset
	LDR r3,=0xfffff000              ; Physic Memory

	IF ttb_cache_on = 1
	LDR r4,=0xffe                    ; Enable Cache
	ELSE
	LDR r4,=0xff2                    ; Disable Cache
	ENDIF

	ADD r3,r3,r4
	STR r3,[r2],#4


;************************************
;* Domain : 0,1,2                   *
;* Mode   : Clinet                  *
;************************************
	MOV r0,#2_010101                ; must define behaviour for domain 1,2,3, set client
	MCR p15,0,r0,c3,c0,0            ; write to CP15 register 3

;************************************
;* Invalidate ICache and DCache     *
;************************************
	MOV r0,#0                       ; clear r0
	MCR p15,0,r0,c7,c7,0            ; Invalidate
	NOP
	NOP
;**********************************
;* Enable Cache                  * 
;**********************************
	MRC p15,0,r0,c1,c0,0
	LDR r1,=0x00001007              ; enable I Cache & D Cache & MMU & Align check
	ORR r0,r0,r1					

;	ORR r0,r0,#(0x1 <<14)           ; enable Round Robin cache replacement
	BIC r0,r0,#(0x1 <<13)           ; disable Hi Vectors

	MCR p15,0,r0,c1,c0,0 
	NOP
	NOP
	MOV pc,lr

	END