hardware.h

arm_uclinux_tools用于安装linux的编译器

#ifndef __ASSEMBLER__
/****************************************  S3C4530 Samsung  UART registers */
struct s3c4530_usart_regs {
  volatile u_32 cr;		/* control		*/
  volatile u_32 csr;		/* channel status	*/
  volatile u_32 ier;		/* interrupt enable	*/
  volatile u_32 thr;		/* tramsmit holding	*/
  volatile u_32 rhr;		/* receive holding	*/
  volatile u_32 brgr;		/* baud rate generator	*/
  volatile u_32 ucc1;		/* control character 1	*/
  volatile u_32 ucc2;		/* control character 2	*/
};
#endif

#define TX_FIFO_DEPTH 32
#define RX_FIFO_DEPTH 32

/****************************************  UART control register */
#define	U_DISABLE_TMODE	0xFFFFFFFC
#define	U_IRQ_TMODE	0x00000001
#define	U_DMA0_TMODE	0x00000002
#define	U_DMA1_TMODE	0x00000003
#define	U_TMODE		0x00000003

#define	U_DISABLE_RMODE	0xFFFFFFF3
#define	U_IRQ_RMODE	0x00000004
#define	U_DMA0_RMODE	0x00000008
#define	U_DMA1_RMODE	0x0000000C
#define	U_RMODE		0x0000000C

#define	U_SBR		0x00000010
#define	U_UCLK		0x00000020
#define	U_ABRD		0x00000040
#define	U_LOOPB		0x00000080

#define	U_NO_PMD	0xFFFFF8FF
#define	U_ODD_PMD	0x00000400
#define	U_EVEN_PMD	0x00000500
#define	U_FC1_PMD	0x00000600
#define	U_FC0_PMD	0x00000700
#define	U_PMD		0x00000700

#define	U_STB		0x00000800

#define	U_WL5		0xFFFFCFFF
#define	U_WL6		0x00001000
#define	U_WL7		0x00002000
#define	U_WL8		0x00003000
#define	U_WL		0x00003000

#define	U_IR		0x00004000
#define	U_TFEN		0x00010000
#define	U_RFEN		0x00020000
#define	U_TFRST		0x00040000
#define	U_RFRST		0x00080000

#define	U_TFTL30	0xFFCFFFFF
#define	U_TFTL24	0x00100000
#define	U_TFTL16	0x00200000
#define	U_TFTL8		0x00300000
#define	U_TFTL		0x00300000

#define	U_RFTL1		0xFF3FFFFF
#define	U_RFTL8		0x00400000
#define	U_RFTL18	0x00800000
#define	U_RFTL28	0x00C00000
#define	U_RFTL		0x00C00000

#define	U_DTR		0x01000000
#define	U_RTS		0x02000000
#define	U_HFEN		0x10000000
#define	U_SFEN		0x20000000

/****************************************  UART status register */
#define	U_TFFUL		(1<<20)
#define	U_TFEMT		(1<<19)
#define	U_THE		(1<<18)
#define	U_TC		(1<<17)
#define	U_E_CTS		(1<<16)
#define	U_CTS		(1<<15)
#define	U_DSR		(1<<14)
#define	U_E_RxTO	(1<<12)
#define	U_RIDLE		(1<<11
#define	U_RFOV		(1<<10)
#define	U_RFFUL		(1<<9)
#define	U_RFEMT		(1<<8)
#define	U_RFREA		(1<<7)
#define	U_DCD		(1<<6)
#define	U_CCD		(1<<5)
#define	U_OER		(1<<4)
#define	U_PER		(1<<3)
#define	U_FER		(1<<2)
#define	U_BSD		(1<<1)
#define	U_RDV		(1)

/****************************************  UART Interrupt Enable register */
#define	U_THEIE		(1<<18)
#define	U_E_CTSIE	(1<<16)
#define	U_E_RxTOIE	(1<<12)
#define	U_OVFFIE	(1<<10)
#define	U_RFREAIE	(1<<7)
#define	U_DCDLIE	(1<<6)
#define	U_CCDIE		(1<<5)
#define	U_OVEIE		(1<<4)
#define	U_PERIE		(1<<3)
#define	U_FERIE		(1<<2)
#define	U_BKDIE		(1<<1)
#define	U_RDRIE		(1)

#define US_ALL_INTS (U_THEIE|U_E_CTSIE|U_E_RxTOIE|U_OVFFIE|U_RFREAIE|U_DCDLIE|U_CCDIE|U_OERIE|U_PERIE|U_FERIE|U_BSDIE|U_RDVIE)

/****************************************  IO -- IO controller */
#define PIO_BASE	IOPMOD


/**************** Bit definitions for IOPMOD, IOPDATA, IOPCON1 */
#define DTR1_PIN	(1<<25)
#define TxD1_PIN	(1<<24)
#define DSR1_PIN	(1<<23)
#define RxD1_PIN	(1<<22)
#define DTR0_PIN	(1<<21)
#define TxD0_PIN	(1<<20)
#define DSR0_PIN	(1<<19)
#define RxD0_PIN	(1<<18)
#define BZ1_PIN		(1<<17)
#define TOUT1_PIN	(1<<17)
#define TOUT0_PIN	(1<<16)
#define nXDACK1_PIN	(1<<15)
#define nXDACK0_PIN	(1<<14)
#define nXDREQ1_PIN	(1<<13)
#define nXDREQ0_PIN	(1<<12)
#define xINTREQ3_PIN	(1<<11)
#define xINTREQ2_PIN	(1<<10)
#define xINTREQ1_PIN	(1<<9)
#define xINTREQ0_PIN	(1<<8)
#define RTS1_PIN	(1<<7)
#define CTS1_PIN	(1<<6)
#define DCD1_PIN	(1<<5)
#define RTS0_PIN	(1<<4)
#define CTS0_PIN	(1<<3)
#define DCD0_PIN	(1<<2)
#define LED_PIN		(1<<1)

/*************************** Bit definitions for IOPCON0 */

#define xINTREQ0_MODE	(3)	/* 0 = level, 1 = rising, 2 = falling, 3 = both */
#define xINTREQ0_FILTER	(1<<2)	/* assert irq if state holds for 3 clocks */
#define xINTREQ0_ACT_HI	(1<<3)	/* 1 = irq active high */
#define xINTREQ0_ENABLE	(1<<4)	/* 1 = enable irq0 on port 8 */

#define xINTREQ1_MODE	(3<<5)
#define xINTREQ1_FILTER	(1<<7)
#define xINTREQ1_ACT_HI	(1<<8)
#define xINTREQ1_ENABLE	(1<<9)	/* 1 = enable irq1 on port 9 */

#define xINTREQ2_MODE	(3<<10)
#define xINTREQ2_FILTER	(1<<12)
#define xINTREQ2_ACT_HI	(1<<13)
#define xINTREQ2_ENABLE	(1<<14)	/* 1 = enable irq2 on port 10 */

#define xINTREQ3_MODE	(3<<15)
#define xINTREQ3_FILTER	(1<<17)
#define xINTREQ3_ACT_HI	(1<<18)
#define xINTREQ3_ENABLE	(1<<19)	/* 1 = enable irq3 on port 11 */

#define nXDREQ0_ACT_HI	(1<<20)	/* 1 = active high */
#define nXDREQ0_FILTER	(1<<21)	/* 1 = 3 clock filtering */
#define nXDREQ0_ENABLE	(1<<22)	/* 1 = enable drq0 on port 12 */

#define nXDREQ1_ACT_HI	(1<<23)
#define nXDREQ1_FILTER	(1<<24)
#define nXDREQ1_ENABLE	(1<<25)	/* 1 = enable drq1 on port 13 */

#define nXDACK0_ACT_HI	(1<<26)
#define nXDACK0_ENABLE	(1<<27)	/* 1 = enable dack0 on port 14 */

#define nXDACK1_ACT_HI	(1<<28)
#define nXDACK1_ENABLE	(1<<29)	/* 1 = enable dack1 on port 15 */



/****************************************  Timer */

#define TIMER_BASE 	TMOD

/* The  S3C4530A has 2 internel 32-bit timers, TC0 and TC1.
 * One of these must be used to drive the kernel's internal
 * timer (the thing that updates jiffies).  Pick a timer channel
 * here.  */
 
#define	KERNEL_TIMER	0

/*  TC mode register */
#define TCLR1		(1<<5)
#define TDM1		(1<<4)
#define TE1		(1<<3)
#define TCLR0		(1<<2)
#define TDM0		(1<<1)
#define TE0		(1)

#ifndef __ASSEMBLER__
struct s3c4530_timer
{
  unsigned long tmr;        // timers mode register      (RW)
  unsigned long tdr0;       // timer0 data register      (RW)
  unsigned long tdr1;       // timer1 data register      (RW)
  unsigned long tcr0;       // timer0 count register      (RW)
  unsigned long tcr1;       // timer1 count register      (RW)
};
#endif

/****************************************  Interrupt Controller */
#define IC_BASE		INTMOD

#define IC_xIRQ0  	(1<<0)
#define IC_xIRQ1  	(1<<1)
#define IC_xIRQ2  	(1<<2)
#define IC_xIRQ3  	(1<<3)
#define IC_UARTTx0  	(1<<4)
#define IC_UARTRxE0  	(1<<5)
#define IC_UARTTx1  	(1<<6)
#define IC_UARTRxE1  	(1<<7)
#define IC_GDMA0  	(1<<8)
#define IC_GDMA1  	(1<<9)
#define IC_TC0  	(1<<10)
#define IC_TC1  	(1<<11)
#define IC_HDLCATx  	(1<<12)
#define IC_HDLCARx  	(1<<13)
#define IC_HDLCBTx  	(1<<14)
#define IC_HDLCBRx  	(1<<15)
#define IC_BDMATx  	(1<<16)
#define IC_BDMARx  	(1<<17)
#define IC_MACTx  	(1<<18)
#define IC_MACRx  	(1<<19)
#define IC_I2C  	(1<<20)
#define IC_GLOBAL  	(1<<21)

#define _IRQ0		0
#define _IRQ1		1
#define _IRQ2		2
#define _IRQ3		3
#define _URTTx0  	4
#define _URTRx0  	5
#define _URTTx1  	6
#define _URTRx1  	7
#define _GDMA0  	8
#define _GDMA1  	9
#define _TC0  		10
#define _TC1  		11
#define _HDLCATx  	12
#define _HDLCARx  	13
#define _HDLCBTx  	14
#define _HDLCBRx  	15
#define _BDMATx  	16
#define _BDMARx  	17
#define _MACTx  	18
#define _MACRx  	19
#define _I2C  		20
#define _GLOBAL		21

#define HW_ETHERNET_ADDR 0x1007fd0

#endif