📄 hardware.h
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/* * uclinux/include/asm-armnommu/arch-evS3C4530HEI/hardware.h * * OZH, 2001 Oleksandr Zhadan. * * This file includes the hardware definitions of EV-S3C4530-HEI board. */ #ifndef __ASM_ARCH_HARDWARE_H#define __ASM_ARCH_HARDWARE_H#include <linux/config.h>#ifndef __ASSEMBLER__typedef unsigned long u_32;#define ARM_CLK ((u_32)(CONFIG_ARM_CLK)) /*(50000000))*/#else#define ARM_CLK CONFIG_ARM_CLK#endif#define MCLK2 (ARM_CLK/2)#define Vol32 *(volatile unsigned int *)#define Vol16 *(volatile unsigned short *)#define Vol08 *(volatile unsigned char *)#define REG_WRITE(addr,data) (Vol32(addr)=(data))#define REG_READ(addr) (Vol32(addr))#ifndef __ASSEMBLER__/**************************************** RAM definitions */#define MAPTOPHYS(a) ((unsigned long)a)#define KERNTOPHYS(a) ((unsigned long)(&a))#define GET_MEMORY_END(p) ((p->u1.s.page_size) * (p->u1.s.nr_pages))#define PARAMS_BASE 0x7000#define HARD_RESET_NOW() { arch_hard_reset(); }#endif#define IO_BASE 0x00000000#define EIO_BASE 0x03600000 /* External I/O banks base address */#define SRB_BASE 0x03FF0000#define BDMA_OWNER 0x80000000#define NON_CACHEABLE 0x04000000/**************************************** System Manager */#define SYSCFG (SRB_BASE+0x0000)#define CLKCON (SRB_BASE+0x3000)#define EXTACON0 (SRB_BASE+0x3008)#define EXTACON1 (SRB_BASE+0x300C)#define EXTDBWTH (SRB_BASE+0x300C)#define ROMCON0 (SRB_BASE+0x3014)#define ROMCON1 (SRB_BASE+0x3018)#define ROMCON2 (SRB_BASE+0x301C)#define ROMCON3 (SRB_BASE+0x3020)#define ROMCON4 (SRB_BASE+0x3024)#define ROMCON5 (SRB_BASE+0x3028)#define DRAMCON0 (SRB_BASE+0x302C)#define DRAMCON1 (SRB_BASE+0x3030)#define DRAMCON2 (SRB_BASE+0x3034)#define DRAMCON4 (SRB_BASE+0x3038)#define REFEXTCON (SRB_BASE+0x303C)/**************************************** Interrupt Controller */#define INTMOD (SRB_BASE+0x4000)#define INTPND (SRB_BASE+0x4004)#define INTMSK (SRB_BASE+0x4008)#define INTPRI0 (SRB_BASE+0x400C)#define INTPRI1 (SRB_BASE+0x4010)#define INTPRI2 (SRB_BASE+0x4014)#define INTPRI3 (SRB_BASE+0x4018)#define INTPRI4 (SRB_BASE+0x401C)#define INTPRI5 (SRB_BASE+0x4020)#define INTOFFSET (SRB_BASE+0x4024)#define INTOSET_FIQ (SRB_BASE+0x4030)#define INTOSET_IRQ (SRB_BASE+0x4034)/**************************************** I/O Ports */#define IOPMOD (SRB_BASE+0x5000)#define IOPCON0 (SRB_BASE+0x5004)#define IOPDATA (SRB_BASE+0x5008)#define IOPCON1 (SRB_BASE+0x500C)/**************************************** Timers */#define TMOD (SRB_BASE+0x6000)#define TDATA0 (SRB_BASE+0x6004)#define TDATA1 (SRB_BASE+0x6008)#define TCNT0 (SRB_BASE+0x600C)#define TCNT1 (SRB_BASE+0x600C)/**************************************** HDLC Channel A */#define HMODE_A (SRB_BASE+0x7000)#define HCON_A (SRB_BASE+0x7004)#define HSTAT_A (SRB_BASE+0x7008)#define HINTEN_A (SRB_BASE+0x700C)#define HTXFIFOC_A (SRB_BASE+0x7010)#define HTXFIFOT_A (SRB_BASE+0x7014)#define HRXFIFO_A (SRB_BASE+0x7018)#define HBRGTC_A (SRB_BASE+0x701C)#define HTPRMB_A (SRB_BASE+0x7020)#define HSAR0_A (SRB_BASE+0x7024)#define HSAR1_A (SRB_BASE+0x7028)#define HSAR2_A (SRB_BASE+0x702C)#define HSAR3_A (SRB_BASE+0x7030)#define HMASK_A (SRB_BASE+0x7034)#define HDMATxPTR_A (SRB_BASE+0x7038)#define HDMARxPTR_A (SRB_BASE+0x703C)#define HMFLR_A (SRB_BASE+0x7040)#define HRBSR_A (SRB_BASE+0x7044)#define HSYNC_A (SRB_BASE+0x7048)#define TCON_A (SRB_BASE+0x704C)/**************************************** HDLC Channel B */#define HMODE_B (SRB_BASE+0x8000)#define HCON_B (SRB_BASE+0x8004)#define HSTAT_B (SRB_BASE+0x8008)#define HINTEN_B (SRB_BASE+0x800C)#define HTXFIFOC_B (SRB_BASE+0x8010)#define HTXFIFOT_B (SRB_BASE+0x8014)#define HRXFIFO_B (SRB_BASE+0x8018)#define HBRGTC_B (SRB_BASE+0x801C)#define HTPRMB_B (SRB_BASE+0x8020)#define HSAR0_B (SRB_BASE+0x8024)#define HSAR1_B (SRB_BASE+0x8028)#define HSAR2_B (SRB_BASE+0x802C)#define HSAR3_B (SRB_BASE+0x8030)#define HMASK_B (SRB_BASE+0x8034)#define HDMATxPTR_B (SRB_BASE+0x8038)#define HDMARxPTR_B (SRB_BASE+0x803C)#define HMFLR_B (SRB_BASE+0x8040)#define HRBSR_B (SRB_BASE+0x8044)#define HSYNC_B (SRB_BASE+0x8048)#define TCON_B (SRB_BASE+0x804C)/**************************************** Ethernet (BDMA) */#define BDMATXCON (SRB_BASE+0x9000)#define BDMARXCON (SRB_BASE+0x9004)#define BDMATXPTR (SRB_BASE+0x9008)#define BDMARXPTR (SRB_BASE+0x900C)#define BDMARXLSZ (SRB_BASE+0x9010)#define BDMASTAT (SRB_BASE+0x9014)#define ETXSTAT (SRB_BASE+0x9040) /* Transmit control frame status */#define CAM (SRB_BASE+0x9100)#define BDMATXBUF (SRB_BASE+0x9200)#define BDMARXBUF (SRB_BASE+0x9800)/**************************************** Ethernet (MAC) */#define MACON (SRB_BASE+0xA000) /* MAC control */#define CAMCON (SRB_BASE+0xA004) /* CAM control */#define MATXCON (SRB_BASE+0xA008) /* Transmit control */#define MATXSTAT (SRB_BASE+0xA00C) /* Transmit status */#define MARXCON (SRB_BASE+0xA010) /* Receive control */#define MARXSTAT (SRB_BASE+0xA014) /* Receive status */#define STADATA (SRB_BASE+0xA018) /* Station management data */#define STACON (SRB_BASE+0xA01C) /* Station management control and address */#define CAMEN (SRB_BASE+0xA028) /* CAM enable */#define EMISSCNT (SRB_BASE+0xA03C) /* Missed error count */#define EPZCNT (SRB_BASE+0xA040) /* Pause count */#define ERMPZCNT (SRB_BASE+0xA044) /* Remote pause count *//**************************************** Ethernet BDMATXCON register map */#define BTxEn 0x00004000 /* BDMA tx enable */#define BTxRs 0x00008000 /* BDMA tx reset *//**************************************** Ethernet BDMARXCON register map */#define BRxEn 0x00004000 /* BDMA rx enable */#define BRxRs 0x00008000 /* BDMA rx reset *//**************************************** Ethernet BDMASTAT register map */#define BRxRDF 0x00000001 /* BDMA received data frame */#define BRxNL 0x00000002 /* BDMA rx null list */#define BRxNO 0x00000004 /* BDMA rx not owner of current frame */#define BRxMSO 0x00000008 /* BDMA rx max size over */#define BRxEmpty 0x00000010 /* BDMA rx buffer empty */#define BRxEarly 0x00000020 /* BDMA rx early length notify *//* reserved */#define BRxFRF 0x00000080 /* BDMA rx early length notify */#define BRxNFR_mask 0x0000ff00 /* BDMA no. frames in rx buf (mask) */#define BRxNFR_shift 8 /* (shift) */#define BTxCCP 0x00010000 /* BDMA tx control packet */#define BTxNL 0x00020000 /* BDMA tx null list */#define BTxNO 0x00040000 /* BDMA tx not owner of current frame *//* reserved */#define BTxEmpty 0x00100000 /* BDMA tx buffer empty *//**************************************** Ethernet tx frame descriptor bits */#define TxCollCnt_mask 0x000f /* # tx collisions */#define TxCollCnt_shift 0#define TxExColl 0x0010 /* 16 collisions occured */#define TxDefer 0x0020 /* transmission defered */#define TxPaused 0x0040 /* transmission paused */#define TxInt 0x0080 /* pkt tx caused an interrupt */#define TxUnder 0x0100 /* tx underrun */#define TxMaxDefer 0x0200 /* tx defered for max_defer */#define TxNCarr 0x0400 /* carrier sense not detected */#define TxSQErr 0x0800 /* SQE error */#define TxLateColl 0x1000 /* tx coll after 512 bit times */#define TxPar 0x2000 /* tx FIFO parity error */#define TxComp 0x4000 /* tx complete or discarded */#define TxHalted 0x8000 /* tx halted OR error *//**************************************** Ethernet MACON register map */#define SwRESET 0x00000040 /* MAC reset *//**************************************** Ethernet CAMCON register map */#define StationAcc 0x00000001 /* Accept Station/Unicast addresses */#define GroupAcc 0x00000002 /* Accept Group/Multicast addresses */#define BroadAcc 0x00000004 /* Accept the Broadcast addresses */#define NegCAM 0x00000008 /* Reject, rather than accept * CAM-recognized entries */#define CompEn 0x00000010 /* Enable compare mode */#define HW_MAX_ADDRS 21 /* CAM consists of 32 words *//**************************************** GDMA Channel 0 */#define GDMACON0 (SRB_BASE+0xB000)#define GDMASRC0 (SRB_BASE+0xB004)#define GDMADST0 (SRB_BASE+0xB008)#define GDMACNT0 (SRB_BASE+0xB00C)/**************************************** GDMA Channel 1 */#define GDMACON1 (SRB_BASE+0xC000)#define GDMASRC1 (SRB_BASE+0xC004)#define GDMADST1 (SRB_BASE+0xC008)#define GDMACNT1 (SRB_BASE+0xC00C)/**************************************** UART Channel 0 */#define UCON0 (SRB_BASE+0xD000)#define USTAT0 (SRB_BASE+0xD004)#define UINTEN0 (SRB_BASE+0xD008)#define UTXBUF0 (SRB_BASE+0xD00C)#define URXBUF0 (SRB_BASE+0xD010)#define UBRDIV0 (SRB_BASE+0xD014)#define UCC1_0 (SRB_BASE+0xD018)#define UCC2_0 (SRB_BASE+0xD01C)/**************************************** UART Channel 1 */#define UCON1 (SRB_BASE+0xE000)#define USTAT1 (SRB_BASE+0xE004)#define UINTEN1 (SRB_BASE+0xE008)#define UTXBUF1 (SRB_BASE+0xE00C)#define URXBUF1 (SRB_BASE+0xE010)#define UBRDIV1 (SRB_BASE+0xE014)#define UCC1_1 (SRB_BASE+0xE018)#define UCC2_1 (SRB_BASE+0xE01C)/**************************************** I2C Bus */#include <asm/arch/i2c.h>/* FIXME USART0_BASE and USART1_BASE should be set in .config */ #define USART0_BASE UCON0 #define USART1_BASE UCON1⌨️ 快捷键说明
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