📄 bsp.c
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/*
*********************************************************************************************************
* MICIRUM BOARD SUPPORT PACKAGE
*
* (c) Copyright 2003-2006; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
* Knowledge of the source code may not be used to write a similar
* product. This file may only be used in accordance with a license
* and should not be redistributed in any way.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* BOARD SUPPORT PACKAGE
*
* Atmel AT91SAM7SE
* on the
* AT91SAM7SE-EK Evaluation Board
*
* Filename : bsp.c
* Version : V1.00
* Programmer(s) : BAN
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#define BSP_GLOBALS
#include <includes.h>
/*
*********************************************************************************************************
* LOCAL DEFINES
*********************************************************************************************************
*/
#define BSP_RAM_REMAP_TEST_BYTE (*(CPU_INT08U *)0x00000030L)
/* ---------------------- GPIOA Pins ---------------------- */
#define GPIOA_LED_POWER DEF_BIT_00 /* (GPIO)( ): Power LED */
#define GPIOA_LED1 DEF_BIT_01 /* (GPIO)( ): LED 1 */
#define GPIOA_LED2 DEF_BIT_02 /* (GPIO)( ): LED 2 */
#define GPIOA_TWD DEF_BIT_03 /* TWI (A): EEPROM AT24C256 (SDA) */
#define GPIOA_TWCK DEF_BIT_04 /* TWI (A): EEPROM AT24C256 (SCL) */
#define GPIOA_RXD0 DEF_BIT_05 /* US0 (A): RS232 COM Port */
#define GPIOA_TXD0 DEF_BIT_06 /* US0 (A): RS232 COM Port */
#define GPIOA_RTS0 DEF_BIT_07 /* US0 (A): RS232 COM Port */
#define GPIOA_CTS0 DEF_BIT_08 /* US0 (A): RS232 COM Port */
#define GPIOA_DRXD DEF_BIT_09 /* DBGU (A): Serial Debug Port */
#define GPIOA_DTXD DEF_BIT_10 /* DBGU (A): Serial Debug Port */
#define GPIOA_NPCS0 DEF_BIT_11 /* SPI (A): SPI Dataflash (Chip Select) */
#define GPIOA_MISO DEF_BIT_12 /* SPI (A): SPI Dataflash & Audio DAC */
#define GPIOA_MOSI DEF_BIT_13 /* SPI (A): SPI Dataflash & Audio DAC */
#define GPIOA_SPCK DEF_BIT_14 /* SPI (A): SPI Dataflash & Audio DAC */
#define GPIOA_TF DEF_BIT_15 /* (A): Audio DAC AT73C213 (LRFS) */
#define GPIOA_TK DEF_BIT_16 /* (A): Audio DAC AT73C213 (BCLK) */
#define GPIOA_TD DEF_BIT_17 /* (A): Audio DAC AT73C213 (SDIN) */
#define GPIOA_NCS2_CFCS2 DEF_BIT_20 /* (GPIO)( ): Ethernet DM9000A (Chip Select) */
#define GPIOA_NWR1_NBS1_CFIOR DEF_BIT_23 /* SDRAM (B): SDRAM Device (NBS1) */
#define GPIOA_SDA10 DEF_BIT_24 /* SDRAM (B): SDRAM Device (SDA10) */
#define GPIOA_SDCKE DEF_BIT_25 /* SDRAM (B): SDRAM Device (SDCKE) */
#define GPIOA_NCS1_SDCS DEF_BIT_26 /* SDRAM (B): SDRAM Device (Chip Select) */
#define GPIOA_SDWE DEF_BIT_27 /* SDRAM (B): SDRAM Device (SDWE) */
#define GPIOA_CAS DEF_BIT_28 /* SDRAM (B): SDRAM Device (CAS0) */
#define GPIOA_RAS DEF_BIT_29 /* SDRAM (B): SDRAM Device (RAS) */
#define GPIOA_IRQ1 DEF_BIT_30 /* (GPIO)( ): Ethernet DM9000A (IRQ) */
#define GPIOA_NPCS1 DEF_BIT_31 /* (A): SPI Audio DAC AT73C213 (Chip Select) */
/* ---------------------- GPIOB Pins ---------------------- */
#define GPIOB_EBI_A (0x0003FFFF) /* EBI (A): EBI Address Bus */
#define GPIOB_NANDCS DEF_BIT_18 /* (GPIO)( ): NandFlash (NANDCS) */
#define GPIOB_RDYBSY DEF_BIT_19 /* (GPIO)( ): NandFlash (RDYBSY) */
#define GPIOB_PB2 DEF_BIT_22 /* (GPIO)( ): PB2 */
#define GPIOB_PB1 DEF_BIT_25 /* (GPIO)( ): PB1 */
#define GPIOB_JOY_UP DEF_BIT_23 /* (GPIO)( ): Joystick Up */
#define GPIOB_JOY_DOWN DEF_BIT_24 /* (GPIO)( ): Joystick Down */
#define GPIOB_JOY_RIGHT DEF_BIT_26 /* (GPIO)( ): Joystick Right */
#define GPIOB_JOY_LEFT DEF_BIT_27 /* (GPIO)( ): Joystick Left */
#define GPIOB_PCK2 DEF_BIT_28 /* (A): Audio DAC AT73C213 (MCLK) */
/* ---------------------- GPIOC Pins ---------------------- */
#define GPIOC_EBI_D (0x0000FFFF) /* EBI (D): EBI Data Bus */
#define GPIOC_NANDOE DEF_BIT_17 /* NAND (B): NandFlash (NANDOE) */
#define GPIOC_NANDWE DEF_BIT_18 /* NAND (B): NandFlash (NANDWE) */
#define GPIOC_USB_CNX DEF_BIT_19 /* (GPIO)( ): USB_CNX (VBUS Detect) */
#define GPIOC_NAND_CLE DEF_BIT_22 /* (GPIO)( ): NandFlash (CLE) */
/*
*********************************************************************************************************
* LOCAL CONSTANTS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL DATA TYPES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL TABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL GLOBAL VARIABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL FUNCTION PROTOTYPES
*********************************************************************************************************
*/
static void LED_Init (void);
static void PB_Init (void);
static void Joystick_Init (void);
static void Tmr_TickInit (void);
static void BSP_DummyISR_Handler (void);
static void PLL_Init (void);
static void BSP_IntCtrlInit (void);
/*
*********************************************************************************************************
* LOCAL CONFIGURATION ERRORS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*********************************************************************************************************
** GLOBAL FUNCTIONS
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* BSP_Init()
*
* Description : Initialize the Board Support Package (BSP).
*
* Argument(s) : none.
*
* Return(s) : none.
*
* Note(s) : (1) This function SHOULD be called before any other BSP function is called.
*********************************************************************************************************
*/
void BSP_Init (void)
{
AT91C_BASE_WDTC->WDTC_WDMR |= AT91C_WDTC_WDDIS; /* Disable the Watchdog Timer */
/* Enable the hardware reset button */
AT91C_BASE_RSTC->RSTC_RMR |= (CPU_INT32U)(0xA5 << 24) | AT91C_RSTC_URSTEN;
PLL_Init(); /* Initialize the PLL and select it for MCLK */
LED_Init(); /* Initialize the I/Os for the LEDs */
PB_Init(); /* Initialize the I/Os for the push buttons */
Joystick_Init(); /* Initialize the I/Os for the joystick */
BSP_IntCtrlInit(); /* Initialize the Interrupt Controller */
Tmr_TickInit(); /* Initialize uC/OS-II's Tick Rate */
}
/*
*********************************************************************************************************
* BSP_CPU_ClkFreq()
*
* Description : Get the master clock frequency (MCK) (which is also the processor clock frequency (PCK)).
*
* Argument(s) : none.
*
* Return(s) : The CPU clock frequency, in Hz.
*********************************************************************************************************
*/
CPU_INT32U BSP_CPU_ClkFreq (void)
{
CPU_INT32U mckr_css;
CPU_INT32U pll_mult;
CPU_INT32U pll_div;
CPU_INT32U mclk_div;
CPU_INT32U cpu_freq;
/* ------------------ MASTER CLOCK INPUT ------------------ */
mckr_css = (AT91C_BASE_PMC->PMC_MCKR) & 0x00000003;
switch (mckr_css) {
case 0x00: /* Slow clock */
cpu_freq = SLOW_XTAL_FREQ;
break;
case 0x01: /* Main clock */
cpu_freq = MAIN_XTAL_FREQ;
break;
case 0x02: /* Reserved */
cpu_freq = 0;
break;
case 0x03: /* PLL clock */
pll_mult = (AT91C_BASE_CKGR->CKGR_PLLR & 0x07FF0000) >> 16;
pll_div = (AT91C_BASE_CKGR->CKGR_PLLR & 0x000000FF) >> 0;
if (pll_div == 0) {
cpu_freq = 0; /* If PLL divider is zero, then PLL output is zero. */
} else if (pll_mult == 0) {
cpu_freq = MAIN_XTAL_FREQ; /* If PLL multiplier is zero, then PLL is disabled. */
} else {
cpu_freq = (MAIN_XTAL_FREQ / pll_div) * (pll_mult + 1);
}
break;
}
/* ---------------- MASTER CLOCK PRESCALER ---------------- */
/* Read the Master Clock divider */
mclk_div = (AT91C_BASE_PMC->PMC_MCKR >> 2) & 0x07;
mclk_div = 1 << mclk_div; /* Convert 0-7 into 1, 2, 4, 8, 16, 32, or 64 */
if (mclk_div >= 128) { /* Divider pattern for 128 is reserved */
return (cpu_freq);
}
cpu_freq = cpu_freq / mclk_div;
return (cpu_freq);
}
/*
*********************************************************************************************************
* OS_CPU_ExceptHndlr()
*
* Description : Handle any exceptions.
*
* Argument(s) : except_id ARM exception type:
*
* OS_CPU_ARM_EXCEPT_RESET 0x00
* OS_CPU_ARM_EXCEPT_UNDEF_INSTR 0x01
* OS_CPU_ARM_EXCEPT_SWI 0x02
* OS_CPU_ARM_EXCEPT_PREFETCH_ABORT 0x03
* OS_CPU_ARM_EXCEPT_DATA_ABORT 0x04
* OS_CPU_ARM_EXCEPT_ADDR_ABORT 0x05
* OS_CPU_ARM_EXCEPT_IRQ 0x06
* OS_CPU_ARM_EXCEPT_FIQ 0x07
*
* Return(s) : none.
*
* Caller(s) : OS_CPU_ARM_EXCEPT_HANDLER(), which is declared in os_cpu_a.s.
*********************************************************************************************************
*/
void OS_CPU_ExceptHndlr (CPU_INT32U except_id)
{
CPU_FNCT_VOID pfnct;
CPU_INT32U *sp;
if (except_id == OS_CPU_ARM_EXCEPT_IRQ) {
pfnct = (CPU_FNCT_VOID)AT91C_BASE_AIC->AIC_IVR; /* Read the interrupt vector from the VIC */
while (pfnct != (CPU_FNCT_VOID)0) { /* Make sure we don't have a NULL pointer */
(*pfnct)(); /* Execute the ISR for the interrupting device */
AT91C_BASE_AIC->AIC_EOICR = 0; /* End of handler */
pfnct = (CPU_FNCT_VOID)(AT91C_BASE_AIC->AIC_IVR); /* Read IRQ hanlder from the AIC */
}
AT91C_BASE_AIC->AIC_EOICR = 0; /* End of handler */
} else if (except_id == OS_CPU_ARM_EXCEPT_FIQ) {
pfnct = (CPU_FNCT_VOID)AT91C_BASE_AIC->AIC_FVR; /* Read the interrupt vector from the VIC */
while (pfnct != (CPU_FNCT_VOID)0) { /* Make sure we don't have a NULL pointer */
(*pfnct)(); /* Execute the ISR for the interrupting device */
AT91C_BASE_AIC->AIC_EOICR = 0; /* End of handler */
pfnct = (CPU_FNCT_VOID)(AT91C_BASE_AIC->AIC_FVR); /* Read FIQ handler from the AIC */
}
AT91C_BASE_AIC->AIC_EOICR = 0; /* End of handler */
} else {
sp = (CPU_INT32U *)OSTCBCur->OSTCBStkPtr;
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