nand.c

基于sumsung s3c2440a的nboot 源码

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
--*/
#include <string.h>

#include "def.h"
#include "option.h"
#include "2440addr.h"
#include "2440lib.h"
#include "nand.h"

void __RdPage512(UCHAR *bufPt); 
void __RdPage256(UCHAR *bufPt); 

//  Status bit pattern
#define STATUS_READY                0x40          
#define STATUS_ERROR                0x01

#define NF_CMD(cmd)	    {rNFCMD  = (cmd); }
#define NF_ADDR(addr)	{rNFADDR = (addr); }	
#define NF_nFCE_L()	    {rNFCONT &= ~(1<<1); }
#define NF_nFCE_H()	    {rNFCONT |= (1<<1); }
#define NF_RSTECC()	    {rNFCONT |= (1<<4); }
#if (K9F1G08_SUPPORT||K9F2G08_SUPPORT||K9F4G08_SUPPORT||K9F8G08_SUPPORT)
#define NF_RDDATA()		((*(volatile unsigned*)0x4E000010) )
#else
#define NF_RDDATA() 	(rNFDATA)
#endif
#define NF_WRDATA(data) {rNFDATA = (data); }
#define NF_WAITRB()     {while(!(rNFSTAT&(1<<0)));} 
#define NF_CLEAR_RB()	{rNFSTAT |= (1<<2); }
#define NF_DETECT_RB()	{while(!(rNFSTAT&(1<<2)));}
#define NF_MECC_UnLock()	{rNFCONT &= ~(1<<5);}
#define NF_MECC_Lock()		{rNFCONT |= (1<<5);}

#define     pNFCONF     rNFCONF 
#define     pNFCMD      rNFCMD  
#define     pNFADDR     rNFADDR 
#define     pNFDATA     rNFDATA 
#define     pNFSTAT     rNFSTAT 
#define     pNFECC      rNFECC0  

#define NF_CE_L()     NF_nFCE_L()
#define NF_CE_H()     NF_nFCE_H()
#define NF_DATA_R()   rNFDATA
#define NF_ECC()      rNFECC0
#define NF_RDDATA8() 		((*(volatile unsigned char*)0x4E000010) )
typedef union _ECCRegVal
{
	DWORD	dwECCVal;
	BYTE	bECCBuf[4];
} ECCRegVal;

#if (K9F1G08_SUPPORT||K9F2G08_SUPPORT||K9F4G08_SUPPORT||K9F8G08_SUPPORT)
#define NFDATA 0x4E000010
#define C_LANG	1
#define DMA		2
#define TRANS_MODE 2
#else
#define AdvFlash        0
#endif
//
//  Reset the chip
//
void NF_Reset()
{                       
    NF_CE_L();
	NF_CLEAR_RB();
    NF_CMD(CMD_RESET);  
    NF_DETECT_RB(); 
    NF_CE_H();          
}

// HCLK=133Mhz
#define TACLS		0
#define TWRPH0		6
#define TWRPH1		0

void NF_Init(void)
{
    rNFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<0);
    rNFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(0<<6)|(0<<5)|(1<<4)|(1<<1)|(1<<0);
    rNFSTAT = 0;
}

#if (NF_READID == 1)
void NF_ReadID()
{
    USHORT  wData1, wData2;

    //  First we enable chip select
    NF_CE_L();
	NF_CLEAR_RB();

    //  Issue commands to the controller
    NF_CMD(CMD_READID);
    NF_ADDR(0x00);

    NF_DETECT_RB();

    wData1 = (BYTE)NF_DATA_R();
    wData2 = (BYTE)NF_DATA_R();

    NF_CE_H();

    Uart_SendString("Nand Mfg: ");
    Uart_SendDWORD((DWORD)wData1, TRUE);
    Uart_SendString("Nand Dev: ");
    Uart_SendDWORD((DWORD)wData2, TRUE);
}
#endif

#ifdef READ_SECTOR_INFO
/* 
 *  NAND_ReadSectorInfo
 *
 *  Read SectorInfo out of the spare area. The current implementation only handles
 *  one sector at a time.
 */
void 
NAND_ReadSectorInfo(
    SECTOR_ADDR sectorAddr, 
    PSectorInfo pInfo
    )
{
    //  Chip enable
    NF_CE_L();
	NF_CLEAR_RB();

    //  Write the command
    NF_CMD(CMD_READ2);

    //  Write the address
    NF_ADDR(0x00);
    NF_ADDR(sectorAddr & 0xff);
    NF_ADDR((sectorAddr >> 8) & 0xff);
    
    if (NEED_EXT_ADDR) {
        NF_ADDR((sectorAddr >> 16) & 0xff);
    }

    //  Wait for the Ready bit
    NF_DETECT_RB();

    //  Read the SectorInfo data (we only need to read first 8 bytes) 
    pInfo->dwReserved1  = (DWORD) ((BYTE) NF_DATA_R()) << 24;
    pInfo->dwReserved1 |= (DWORD) ((BYTE) NF_DATA_R()) << 16;
    pInfo->dwReserved1 |= (DWORD) ((BYTE) NF_DATA_R()) << 8;
    pInfo->dwReserved1 |= (DWORD) ((BYTE) NF_DATA_R());

    //  OEM byte
    pInfo->bOEMReserved = (BYTE) NF_DATA_R();

    //  Read the bad block mark
    pInfo->bBadBlock = (BYTE) NF_DATA_R();
    
    //  Second reserved field (WORD)
    pInfo->wReserved2 = ((BYTE) NF_DATA_R() << 8);
    pInfo->wReserved2 |= ((BYTE) NF_DATA_R());

    NF_CE_H();
}
#endif


//  FMD_ReadSector
//
//  Read the content of the sector.
//
//  startSectorAddr: Starting page address
//  pSectorBuff  : Buffer for the data portion
//  pSectorInfoBuff: Buffer for Sector Info structure
//  dwNumSectors : Number of sectors
//
BOOL 
FMD_ReadSector(
    SECTOR_ADDR startSectorAddr, 
    LPBYTE pSectorBuff,
    PSectorInfo pSectorInfoBuff, 
    DWORD dwNumSectors
    )
{
    DWORD   i, r = 0;
    BYTE   ecc0,ecc1,ecc2;
    BOOL   rc = TRUE;
    ECCRegVal eccRegVal;

    //  BUGBUGBUG: I need to come back to support dwNumSectors > 1
    //
    //  Sanity check
    if (!pSectorBuff && !pSectorInfoBuff || dwNumSectors > 1 || !pSectorBuff) {
//        Uart_SendString("ERROR_INVALID_PARAMETER\n");
        return FALSE;
    }

//    Uart_SendString("R: ");
//    Uart_SendDWORD(startSectorAddr, TRUE);

    //  Initialize ECC register
    NF_RSTECC();
	NF_MECC_UnLock();

    //  Enable the chip
    NF_nFCE_L();   
	NF_CLEAR_RB();

    // Issue Read command
    NF_CMD(CMD_READ);
#if (K9F1G08_SUPPORT||K9F2G08_SUPPORT||K9F4G08_SUPPORT||K9F8G08_SUPPORT)
	NF_ADDR(0);	// Column (A[7:0]) = 0
	NF_ADDR(0);		// A[11:8]
	NF_ADDR((startSectorAddr)&0xff);	// A[19:12]
	NF_ADDR((startSectorAddr>>8)&0xff);	// A[27:20]
	#if(!K9F1G08_SUPPORT)	//if the flash is not K9F1G08,then need the 3thd row address.
	NF_ADDR((startSectorAddr>>16)&0xff);	// A[30:28]
	#endif	  
	 NF_CMD(0x30);	// 2'nd command
	 NF_DETECT_RB();
		
      #if TRANS_MODE==C_LANG
			for(i=0;i<2048;i++) {
				*pSectorBuff++=NF_RDDATA8();	// Read one page
			}
      #elif TRANS_MODE==DMA
			// Nand to memory dma setting
			rSRCPND=BIT_DMA0;	// Init DMA src pending.
			rDISRC0=NFDATA; 	// Nand flash data register
			rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
			rDIDST0=(unsigned)pSectorBuff;
			rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
			rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4/4);
			//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
	
			// DMA on and start.
			rDMASKTRIG0=(1<<1)|(1<<0);
	
			while(!(rSRCPND & BIT_DMA0));	// Wait until Dma transfer is done.
			
			rSRCPND=BIT_DMA0;
	
      #endif
	
	  	 NF_MECC_Lock();
	
	
	//	 NF_RDDATA8();
	//	 Mecc=NF_RDDATA();
	//	 rNFECC=((Mecc&0xff00)<<8)|(Mecc&0xff);
	//	 rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
		
	
		 NF_nFCE_H();	 
	
	//	 if ((rNFESTAT0&0x3) == 0x0){			
			return TRUE;
	//	 }
	//	 else {
	//		   return FALSE;
	//	 }
#else
    //  Set up address
    NF_ADDR(0x00);
    NF_ADDR((startSectorAddr) & 0xff);
    NF_ADDR((startSectorAddr >> 8) & 0xff);
    if (NEED_EXT_ADDR) {
        NF_ADDR((startSectorAddr >> 16) & 0xff);
    }

    for (i = 0; i < 5; i++);   // wait tWB(100ns)

    NF_DETECT_RB();        // wait tR(max 12us)

    // read the data
    __RdPage512(pSectorBuff);

	NF_MECC_Lock();


	//	Read the ECC from ECC Register
	eccRegVal.dwECCVal = NF_ECC();

	//	Skip first 8 bytes
	for(i=0; i<8; i++){
		ecc0 = (BYTE)NF_DATA_R();
	}
	
	ecc0 = (BYTE)NF_DATA_R();
	ecc1 = (BYTE)NF_DATA_R();
	ecc2 = (BYTE)NF_DATA_R();
	
    NF_nFCE_H();
    
    if ( startSectorAddr < 0x120 ) // NO ECC Check about EBOOT
    {
    	rc = TRUE;
    }
    else
    {
	if(	ecc0 != eccRegVal.bECCBuf[0] ||
		ecc0 != eccRegVal.bECCBuf[0] ||
		ecc0 != eccRegVal.bECCBuf[0] )  {
//		Uart_SendString("ECC mismatch for Sector: ");
//		Uart_SendDWORD(startSectorAddr, TRUE);
		rc = FALSE;
	}
    }
#endif
    return rc;
}