📄 hvwdefines.h
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// hvwdefines
// build 004, engines forward/reverse swapped
// build 005, explanation comment added
/*
Question:
Why is this long include file needed?
Answer:
The Asuro programming examples use something like this:
#define FWD (1 << PB5)
If I like to create a new program or modify any of my own existing programs
if find it difficult to understand what all of this ment to be. So I need
to re-read the Atmega8 pdf documentation
I develooped my own way of setting, clearing and reading bits from various
registers in such a way that I easily could understand my own programs at a
later time when I all forgot about my program.
-----o-----
I use a lot of 'defines'. For example:
#define PB5_L (0x20<<8)
this converts PB5_L (a bit that must be cleared) into hex value 0x2000 (shifts it to the high byte part)
#define PB5_H (0x20)
this converts PB5_H (a bit that must be set ) into hex value 0x0020 (low byte part)
-----o-----
Now my 'defined' SFRX function (defined near the end of this file) may be written like
SFRX ( PORTB , PB4_L | PB5_H | PB1_L ) ;
This function will set bit 4 and bit 1 to LOW and bit 5 to HIGH in port PORTB.
This function is executed by the preprocessor and therefore will NOT create more
microcontroller code as when using the ASURO way of programming.
-----o-----
Port PB5 controls the right Asuro engine, when LOW it enables the right engine to
move reverse and PB4 must be HIGH.
#define PB5_L (0x20<<8) setting PortB bit5 low is converted to hex 0x2000 (high byte part of 16-bit integer) (PORTB)
#define PB5_H (0x20) setting PortB bit5 high is converted to hex 0x0020 (low byte part of 16-bit integer) (PORTB)
#define PB5_I PB5_L setting a bit as (I)nput equals setting that bit (in DDRB, not PORTB) to (L)ow
#define PB5_O PB5_H setting a bit as (O)utput equals setting that bit (in DDRB, not PORTB) to (H)igh
#define REV_RGT_L PB5_L activate reversing right engine (remember that active = LOW in case of engine control) (PORTB)
#define REV_RGT_H PB5_H inactivate reversing right engine (remember that inactive = HIGH in case of engine control) (PORTB)
#define REV_RGT_I PB5_L setting right engine microcontroller pin as (I)nput (DDRB)
#define REV_RGT_O PB5_H setting right engine microcontroller pin as (O)utput (DDRB)
#define REV_RGT_N PB5_L deselection (N)one/(N)eutral pull-up resistor at right engine microcontroller pin (PORTB)
#define REV_RGT_P PB5_H selection (P)ull-up pull-up resistor at right engine microcontroller pin (PORTB)
if you like to use PORT bitnames you may use PB5_n bitnaming and if you like to use
port-related Asuro-names you may use REV_RGT_n bit naming. Both do the same.
-----o-----
If I want to switch left engine to (output and) forward I may program: (bit 5 must be low and bit 4 must be high)
SFRX ( DDRB , PB5_O | PB4_O ) ; //switch ports pb4 and pb5 as outputs
SFRX ( PORTB , PB5_L | PB4_H ) ; //switch port pb5 low and pb4 high
or
SFRX ( DDRB , REV_RGT_O | FWD_RGT_O ) ; //swithc ports pb4 and pb5 as outputs
SFRX ( PORTB , REV_RGT_L | FWD_RGT_H ) ; //switch port pb5 low and pb4 high
the bit position in the SFRX function is irrelevant, see below.
SFRX ( PORTB , PB5_L | PB4_H ) ; //switch port pb5 low and pb4 high
SFRX ( PORTB , PB4_H | PB5_L ) ; //switch port pb5 low and pb4 high
-----o-----
This way of programming is not watertide (I know) and may be confusing,
for example:
SFRX ( DDRB , REV_RGT_L ) ;
will set Port PB5 to INPUT and not to LOW because REV_RGT_L is ment to be used
with PORTB and not with DDRB!
No compiler warning or whatsoever is given.
-----o-----
*/
#ifndef _HVW_DEFINES_H_
#define _HVW_DEFINES_H_ 1
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/signal.h>
#define FALSE 0
#define TRUE 1
/*
_BV(b) equals (1<<b), meaning, tranfer bitnumber to byte-with-bit-in-specified-byte-bit--position
Each byte is then transferred to the high part of an integer if it is a SET bit.
Each byte is then transferred to the low part of an integer if it is a CLR bit.
Example:
PUD = 2
_BV(PUD) = 0x04
PUD_L = 0x0004 to be cleared
PUD_H = 0x0400 to be set
The inline function will find the set-bits at NN position as 0xNN00
The inline function will find the clr-bits at NN position as 0x00NN
*/
//GICR
#define INT1_L (0x80<<8)
#define INT1_H (0x80)
#define INT0_L (0x40<<8)
#define INT0_H (0x40)
//TCCR2, 0x25
#define FOC2_L (0x80<<8)
#define FOC2_H (0x80)
#define WGM20_L (0x40<<8)
#define WGM20_H (0x40)
#define COM21_L (0x20<<8)
#define COM21_H (0x20)
#define COM20_L (0x10<<8)
#define COM20_H (0x10)
#define WGM21_L (0x08<<8)
#define WGM21_H (0x08)
#define CS22_L (0x04<<8)
#define CS22_H (0x04)
#define CS21_L (0x02<<8)
#define CS21_H (0x02)
#define CS20_L (0x01<<8)
#define CS20_H (0x01)
//TIMSK
#define OCIE2_L (0x80<<8)
#define OCIE2_H (0x80)
#define TOIE2_L (0x40<<8)
#define TOIE2_H (0x40)
#define TICIE1_L (0x20<<8)
#define TICIE1_H (0x20)
#define OCIE1A_L (0x10<<8)
#define OCIE1A_H (0x10)
#define OCIE1B_L (0x08<<8)
#define OCIE1B_H (0x08)
#define TOIE1_L (0x04<<8)
#define TOIE1_H (0x04)
//not available
//not available
#define TOIE0_L (0x01<<8)
#define TOIE0_H (0x01)
//SPMCR
#define SPMIE_L (0x80<<8)
#define SPMIE_H (0x80)
#define RWWSB_L (0x40<<8)
#define RWWSB_H (0x40)
#define NONE5_L (0x20<<8)
#define NONE5_H (0x20)
#define RWWSRE_L (0x10<<8)
#define RWWSRE_H (0x10)
#define BLBSET_L (0x08<<8)
#define BLBSET_H (0x08)
#define PGWRT_L (0x04<<8)
#define PGWRT_H (0x04)
#define PGERS_L (0x02<<8)
#define PGERS_H (0x02)
#define SPMEM_L (0x01<<8)
#define SPMEM_H (0x01)
//SFIOR
#define ACME_L (0x08<<8)
#define ACME_H (0x08)
#define PUD_L (0x04<<8)
#define PUD_H (0x04)
#define PSR2_L (0x02<<8)
#define PSR2_H (0x02)
#define PSR10_L (0x01<<8)
#define PSR10_H (0x01)
//SREG
#define GIE_L (0x80<<8)
#define GIE_H (0x80)
//ACSR
#define ACD_L (0x80<<8)
#define ACD_H (0x80)
#define ACBG_L (0x40<<8)
#define ACBG_H (0x40)
#define ACO_L (0x20<<8)
#define ACO_H (0x20)
#define ACI_L (0x10<<8)
#define ACI_H (0x10)
#define ACIE_L (0x08<<8)
#define ACIE_H (0x08)
#define ACIC_L (0x04<<8)
#define ACIC_H (0x04)
#define ACIS1_L (0x02<<8)
#define ACIS1_H (0x02)
#define ACIS0_L (0x01<<8)
#define ACIS0_H (0x01)
//ADMUX
#define REFS1_L (0x80<<8)
#define REFS1_H (0x80)
#define REFS0_L (0x40<<8)
#define REFS0_H (0x40)
#define ADLAR_L (0x20<<8)
#define ADLAR_H (0x20)
#define NONE4_L (0x10<<8)
#define NONE4_H (0x10)
#define MUX3_L (0x08<<8)
#define MUX3_H (0x08)
#define MUX2_L (0x04<<8)
#define MUX2_H (0x04)
#define MUX1_L (0x02<<8)
#define MUX1_H (0x02)
#define MUX0_L (0x01<<8)
#define MUX0_H (0x01)
//ADCSRA
#define ADEN_L (0x80<<8)
#define ADEN_H (0x80)
#define ADSC_L (0x40<<8)
#define ADSC_H (0x40)
#define ADFR_L (0x20<<8)
#define ADFR_H (0x20)
#define ADIF_L (0x10<<8)
#define ADIF_H (0x10)
#define ADIE_L (0x08<<8)
#define ADIE_H (0x08)
#define ADPS2_L (0x04<<8)
#define ADPS2_H (0x04)
#define ADPS1_L (0x02<<8)
#define ADPS1_H (0x02)
#define ADPS0_L (0x01<<8)
#define ADPS0_H (0x01)
//TCCR0
#define CS02_L (0x04<<8)
#define CS02_H (0x04)
#define CS01_L (0x02<<8)
#define CS01_H (0x02)
#define CS00_L (0x01<<8)
#define CS00_H (0x01)
//TCCR1A
#define COM1A1_L (0x80<<8)
#define COM1A1_H (0x80)
#define COM1A0_L (0x40<<8)
#define COM1A0_H (0x40)
#define COM1B1_L (0x20<<8)
#define COM1B1_H (0x20)
#define COM1B0_L (0x10<<8)
#define COM1B0_H (0x10)
#define FOC1A_L (0x08<<8)
#define FOC1A_H (0x08)
#define FOC1B_L (0x04<<8)
#define FOC1B_H (0x04)
#define WGM11_L (0x02<<8)
#define WGM11_H (0x02)
#define WGM10_L (0x01<<8)
#define WGM10_H (0x01)
//TCCR1B
#define ICNC1_L (0x80<<8)
#define ICNC1_H (0x80)
#define ICES1_L (0x40<<8)
#define ICES1_H (0x40)
#define RSRVD5_L (0x20<<8)
#define RSRVD5_H (0x20)
#define WGM13_L (0x10<<8)
#define WGM13_H (0x10)
#define WGM12_L (0x08<<8)
#define WGM12_H (0x08)
#define CS12_L (0x04<<8)
#define CS12_H (0x04)
#define CS11_L (0x02<<8)
#define CS11_H (0x02)
#define CS10_L (0x01<<8)
#define CS10_H (0x01)
//TCCR2
#define FOC2_L (0x80<<8)
#define FOC2_H (0x80)
#define WGM20_L (0x40<<8)
#define WGM20_H (0x40)
#define COM21_L (0x20<<8)
#define COM21_H (0x20)
#define COM20_L (0x10<<8)
#define COM20_H (0x10)
#define WGM21_L (0x08<<8)
#define WGM21_H (0x08)
#define CS22_L (0x04<<8)
#define CS22_H (0x04)
#define CS21_L (0x02<<8)
#define CS21_H (0x02)
#define CS20_L (0x01<<8)
#define CS20_H (0x01)
//UCSRA
#define RXC_L (0x80<<8)
#define RXC_H (0x80)
#define TXC_L (0x40<<8)
#define TXC_H (0x40)
#define UDRE_L (0x20<<8)
#define UDRE_H (0x20)
#define FE_L (0x10<<8)
#define FE_H (0x10)
#define DOR_L (0x08<<8)
#define DOR_H (0x08)
#define PE_L (0x04<<8)
#define PE_H (0x04)
#define U2X_L (0x02<<8)
#define U2X_H (0x02)
#define MPCM_L (0x01<<8)
#define MPCM_H (0x01)
//UCSRB
#define RXCIE_L (0x80<<8)
#define RXCIE_H (0x80)
#define TXCIE_L (0x40<<8)
#define TXCIE_H (0x40)
#define UDRIE_L (0x20<<8)
#define UDRIE_H (0x20)
#define RXEN_L (0x10<<8)
#define RXEN_H (0x10)
#define TXEN_L (0x08<<8)
#define TXEN_H (0x08)
#define UCSZ2_L (0x04<<8)
#define UCSZ2_H (0x04)
#define RXB8_L (0x02<<8)
#define RXB8_H (0x02)
#define TXB8_L (0x01<<8)
#define TXB8_H (0x01)
//UCSRC
#define URSEL_L (0x80<<8)
#define URSEL_H (0x80)
#define UMSEL_L (0x40<<8)
#define UMSEL_H (0x40)
#define UPM1_L (0x20<<8)
#define UPM1_H (0x20)
#define UPM0_L (0x10<<8)
#define UPM0_H (0x10)
#define USBS_L (0x08<<8)
#define USBS_H (0x08)
#define UCSZ1_L (0x04<<8)
#define UCSZ1_H (0x04)
#define UCSZ0_L (0x02<<8)
#define UCSZ0_H (0x02)
#define UCPOL_L (0x01<<8)
#define UCPOL_H (0x01)
//UBRRH
//#define URSEL_L (0x80<<8) allready defined with UCSRC
//#define URSEL_H (0x80) allready defined with UCSRC
#define UBRR11_L (0x08<<8)
#define UBRR11_H (0x08)
#define UBRR10_L (0x04<<8)
#define UBRR10_H (0x04)
#define UBRR09_L (0x02<<8)
#define UBRR09_H (0x02)
#define UBRR08_L (0x01<<8)
#define UBRR08_H (0x01)
//UBRRL
#define UBRR07_L (0x80<<8)
#define UBRR07_H (0x80)
#define UBRR06_L (0x40<<8)
#define UBRR06_H (0x40)
#define UBRR05_L (0x20<<8)
#define UBRR05_H (0x20)
#define UBRR04_L (0x10<<8)
#define UBRR04_H (0x10)
#define UBRR03_L (0x08<<8)
#define UBRR03_H (0x08)
#define UBRR02_L (0x04<<8)
#define UBRR02_H (0x04)
#define UBRR01_L (0x02<<8)
#define UBRR01_H (0x02)
#define UBRR00_L (0x01<<8)
#define UBRR00_H (0x01)
//TIFR
#define OCF2_L (0x80<<8)
#define OCF2_H (0x80)
#define TOV2_L (0x40<<8)
#define TOV2_H (0x40)
#define ICF1_L (0x20<<8)
#define ICF1_H (0x20)
#define OCF1A_L (0x10<<8)
#define OCF1A_H (0x10)
#define OCF1B_L (0x08<<8)
#define OCF1B_H (0x08)
#define TOV1_L (0x04<<8)
#define TOV1_H (0x04)
#define TIFRB1_L (0x02<<8)
#define TIFRB1_H (0x02)
#define TOV0_L (0x01<<8)
#define TOV0_H (0x01)
//PORTB
//+-------+-------+-------+-------+-------+-------+-------+-------+
//| PB7 | PB6 | PB5 | PB4 | PB3 | PB2 | PB1 | PB0 | Port name
//+-------+-------+-------+-------+-------+-------+-------+-------+
//| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | bit number
//+-------+-------+-------+-------+-------+-------+-------+-------+
//| 10 | 9 | 19 | 18 | 17 | 16 | 15 | 14 | pin number
//+-------+-------+-------+-------+-------+-------+-------+-------+
//| XTAL2 | XTAL1 |REV_RGT|FWD_RGT|IR_TXD1|SPD_RGT|SPD_LFT|SLD_GRN| signal name
//+-------+-------+-------+-------+-------+-------+-------+-------+
#define PB7_L (0x80<<8)
#define PB7_H (0x80)
#define PB6_L (0x40<<8)
#define PB6_H (0x40)
#define PB5_L (0x20<<8)
#define PB5_H (0x20)
#define PB4_L (0x10<<8)
#define PB4_H (0x10)
#define PB3_L (0x08<<8)
#define PB3_H (0x08)
#define PB2_L (0x04<<8)
#define PB2_H (0x04)
#define PB1_L (0x02<<8)
#define PB1_H (0x02)
#define PB0_L (0x01<<8)
#define PB0_H (0x01)
#define PB7_I PB7_L
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