📄 asuro 013, remote controlled by rc5.c
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volatile byte gvbRxBitCnt;
volatile long gvlRxDat;
volatile byte gvbSysFlg;
#define SYSTEM_FLAG_RX_IR_CODE 0x01
//================================================================================
// DELAY 50 MICROSECONDS
//================================================================================
void vDelay50us(unsigned int iDel){
//var
unsigned int i;
unsigned char j;
//loop number of 50us loops
for(i=0;i<iDel;i++){
//each bytecount for-loop endures (most probably) 3 times 125ns = 375ns
for(j=0;j<200;j++){
}
}
}
//================================================================================
// INIT ENGINES USING MODE 8 (HvW design)
//================================================================================
void vInitEnginesUsingMode8(void){
//select prescaler /256 = 8Mhz/256/256/2=61Hz=16ms
SFRX(TCCR1B,CS12_H|CS11_L|CS10_L);
//define wgm-mode 8 (ICR1 = TOP)
SFRX(TCCR1A,WGM11_L|WGM10_L);
SFRX(TCCR1B,WGM13_H|WGM12_L);
//OC1A low on upcount-match, high on down-count match
SFRX(TCCR1A,COM1A1_H|COM1A0_L);
//OC1B low on upcount-match, high on down-count match
SFRX(TCCR1A,COM1B1_H|COM1B0_L);
//define TOP count value (0xFFFF=> T period=16ms)
ICR1=255;
//port PB1/OC1A compare count value (left engine off)
OCR1A=0;
//port PB2/OC1B compare count value (right engine off)
OCR1B=0;
}
//================================================================================
// INIT ALL PORTS
//================================================================================
void vInitAllPorts(void){
//disable all output pull-up resistors
SFRX(SFIOR,PUD_H);
//########################################################################################################################
//
//DDRB (= IRTX | LEFT_DIR | PWM | GREEN_LED;)
//initialize Data-Direction-Register-Port-B
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|port name | PB7 | PB6 | PB5 | PB4 | PB3 | PB2 | PB1 | PB0 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|bit number | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|pin number | 10 | 9 | 19 | 18 | 17 | 16 | 15 | 14 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|signal name| XTAL2 | XTAL1 | FWD_RGT | REV_RGT | IR_TXD1 | SPD_RGT | SPD_LFT | SLD_GRN |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
SFRX ( DDRB , FWD_RGT_O | REV_RGT_O | IR_TXD1_O | SPD_RGT_O | SPD_LFT_O | SLD_GRN_O ) ;
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
SFRX ( PORTB , FWD_RGT_H | REV_RGT_L | IR_TXD1_L | SPD_RGT_L | SPD_LFT_L | SLD_GRN_H ) ;
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
// x x . . . . . . = unused (connected to 8MHz Xtal)
// . . n n . . . . = OL OL = both engine poles connected to VCC (break?)
// . . n n . . . . = OL OH = set left engine direction to reverse
// . . OH OL . . . . = OH OL = set left engine direction to forward
// . . n n . . . . = OH OH = both engine poles are equally pulsed if speed is programmed
// . . . . OL . . . = Infra Red transmit signal
// . . . . . OL OL . = left-engine and right-engine speed output
// . . . . . . . OH = system-led green-light control output, ON
//
//########################################################################################################################
//
//DDRC (= ???)
//initialize Data-Direction-Register-Port-C
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|port name | PC7 | PC6 | PC5 | PC4 | PC3 | PC2 | PC1 | PC0 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|bit number | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|pin number | - | 1 | 28 | 27 | 26 | 25 | 24 | 23 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|signal name| - | RESET | VPL_SNS | SWI_JNC | TRS_LFT | TRS_RGT | BOD_LFT | BOD_RGT |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
SFRX ( DDRC , VPL_SNS_I | SWI_JNC_I | TRS_LFT_I | TRS_RGT_I | BOD_LFT_O | BOD_RGT_O ) ;
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
SFRX ( PORTC , VPL_SNS_N | SWI_JNC_N | TRS_LFT_N | TRS_RGT_N | BOD_LFT_L | BOD_RGT_L ) ;
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
// . . IN . . . . . = V+ sensor measurement as input
// . . . IN . . . . = key-press detector as input
// . . . . IN IN . . = left/right track sensors as input
// . . . . , , OL OL = left/right break/odo-meter sensors as input
//
//########################################################################################################################
//
//DDRD (= RIGHT_DIR | FRONT_LED | ODOMETRIE_LED | RED_LED;)
//initialize Data-Direction-Register-Port-D
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|port name | PD7 | PD6 | PD5 | PD4 | PD3 | PD2 | PD1 | PD0 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|bit number | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|pin number | 13 | 12 | 11 | 6 | 5 | 4 | 3 | 2 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
//|signal name| ODO_LDS | FRT_LED | FWD_LFT | REV_LFT | SWI_INT | SLD_RED | IR_RXD | IR_TXD2 |
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
SFRX ( DDRD , ODO_LDS_O | FRT_LED_O | FWD_LFT_O | REV_LFT_O | SWI_INT_I | SLD_RED_O | IR_TXD2_I | IR_RXD_I ) ;
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
SFRX ( PORTD , ODO_LDS_L | FRT_LED_L | FWD_LFT_H | REV_LFT_L | SWI_INT_L | SLD_RED_L | IR_TXD2_L | IR_RXD_L ) ;
//+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
// OL . . . . . . . = both odometrie leds (#001)
// . OL . . . . . . = front (tracking) led (#002)
// . . n n . . . . = OL OL = both engine poles connected to VCC (break?)
// . . n n . . . . = OL OH = set left engine direction to reverse
// . . OH OL . . . . = OH OL = set left engine direction to forward
// . . n n . . . . = OH OH = both engine poles are equally pulsed if speed is programmed
// . . . . IL . . . = 'switches' is input
// . . . . . OL . . = system-led red-light control output
// . . . . . . IL IL = Infra-Red signals both as input
//
//########################################################################################################################
//---init-timer-counter-register-1-for-controlling-engine-speeds---//
//CLK-i/o lijkt 8MHz/2=4MHz te zijn!
//In Waveform Generation Mode 1, 8-bit, TOP = 0xFF = 255
//In prescaler mode 1, Counter clock (CLK-i/o) should be external clock (8MHz) but seems to be external clock / 2 (4MHz)
//Frequency = CLK-i/o / 8 / 256 = 4MHz / 8 / 256 = 2KHz
//TCCR1A Timer Counter 1 Control Register A
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
SFRX ( TCCR1A , COM1A1_H | COM1A0_L | COM1B1_H | COM1B0_L | FOC1A_L | FOC1B_L | WGM11_L | WGM10_H ) ;
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
// n n . . . . . . = 00 : normal port operation
// n n . . . . . . = 01 : toggle OC1A (pin15) on match
// 1 0 . . . . . . = 10 : OC1A (pin15) low on match, high at TOP
// n n . . . . . . = 11 : OC1A (pin15) high on match
// . . n n . . . . = 00 : normal port operation
// . . n n . . . . = 01 : toggle OC1B (pin16) on match
// . . 1 0 . . . . = 10 : OC1B (pin16) low on match, high at TOP
// . . n n . . . . = 11 : OC1B (pin16) high on match
// . . . . 0 0 . . = set to 0 in PWM mode (for compatibility, see pdf page 96)
// . . . . . . 0 1 = nn01 : WGM13-WGM10: Waveform Generation Mode 1, PWM Phase correct 8-bit
// XXnn : see TCCR1B register
//TCCR1B Timer Counter 1 Control Register B
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
SFRX ( TCCR1B , ICNC1_L | ICES1_L | WGM13_L | WGM12_L | CS12_L | CS11_H | CS10_L ) ;
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
// 0 . . . . . . . = no noise-canceler (no 4 clock AD conversion delay)
// . 0 . . . . . . = no input-capture selection
// . . x . . . . . = unused
// . . . 0 0 . . . = 00nn : WGM13-WGM10: Waveform Generation Mode 1 (nnXX : see TCCR1A register)
// . . . . . 0 1 0 = Counterclock = Systemclock / 8
//
//enable compare A timer 1 interrupt
//SFRX ( TIMSK , OCIE1A_H ) ;
//---init-AD-converter-for-measuring-purposes---//
//ADCSRA
//prepair AD-converter, prescaler 64
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
SFRX ( ADCSRA , ADEN_H | ADSC_L | ADFR_L | ADIF_L | ADIE_L | ADPS2_H | ADPS1_H | ADPS0_L ) ;
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
// 1 . . . . . . . = AD-Converter enable
// . 0 . . . . . . = no start AD conversion (not yet)
// . . 0 . . . . . = no free running mode
// . . . 0 . . . . = interrupt (or: conversion finished)
// . . . . 0 . . . = no AD interrupt enable
// . . . . . n n n = ADC prescaler
// . . . . . n n n = 000 = 2, 001=2, 002=4, 003=8, 004=16, 005=32
// . . . . . 1 1 0 = 110 = 64
// . . . . . n n n = 111 = 128
//general interrupt enable
SFRX(SREG,GIE_H);
}
//================================================================================
// INIT USART
// void vInitUsart(unsigned int uiBitRatCod){
//================================================================================
void vInitUsartForRemoteControl(void){
//+-----------+
//| UCSRA | Only bit 6,1,0 are writable
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
SFRX ( UCSRA , RXC_L | TXC_L | UDRE_L | FE_L | DOR_L | PE_L | U2X_L | MPCM_L ) ;
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
// n . . . . . . . = 1 => receive character available
// . 0 . . . . . . = 1 => all data send
// . . n . . . . . = 1 => USART Data Register Empty
// . . . n . . . . = 1 => frame error
// . . . . n . . . = 1 => data overrun
// . . . . . n . . = 1 => parity error
// . . . . . . 0 . = 1 => Double the USART transmission speed
// . . . . . . . 0 = 1 => Multi-processor Communication Mode
//
//+-----------+
//| UCSRB |
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
SFRX ( UCSRB , RXCIE_L | TXCIE_L | UDRIE_L | RXEN_L | TXEN_L | UCSZ2_L | RXB8_L | TXB8_L ) ;
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
// 0 . . . . . . . = RX Complete interrupt enabled
// 0 . . . . . . = TX Complete interrupt disabled
// . . 0 . . . . . = Data Register Empty interrupt disabled
// . . . 0 . . . . = RX disabled
// . . . . 0 . . . = TX disabled
// . . . . . 0 . . = UCSZ2/UCSZ1/UCSZ0 = 011 = 8 databits
// . . . . . . 0 . = RX bit 8 from 0-8 (if 9-bit data enabled)
// . . . . . . . 0 = TX bit 8 from 0-8 (if 9-bit data enabled)
//
//+-----------+
//| UCSRC |
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
SFRX ( UCSRC , URSEL_H | UMSEL_L | UPM1_L | UPM0_L | USBS_L | UCSZ1_L | UCSZ0_L | UCPOL_L ) ;
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
// 1 . . . . . . . = 1 = select UCSRC (this) register
// n . . . . . . . (0 = select UBRRH register)
// . 0 . . . . . . = Select Async mode (=0), 1 = Synchronous mode
// . . 0 0 . . . . = 0 0 Parity Disabled
// . . n n . . . . 0 1 Reserved
// . . n n . . . . 1 0 Parity Enabled, Even Parity
// . . n n . . . . 1 1 Parity Enabled, Odd Parity
// . . . . 0 . . . = 0 = 1stopbit
// . . . . n . . . 1 = 2stopbit
// . . . . . n n . = UCSZ2/UCSZ1/UCSZ0 Databits
// . . . . . n n . = 0=5bit,1=6bit,2=7bit,3=8bit,7=9bit
// . . . . . n n . = 4=reserved,5=reserved,6=reserved
// . . . . . 0 0 . = UCSZ2/UCSZ1/UCSZ0 Databits
// . . . . . . . 0 = clock polarity:
// 0=Rising TX-XCK Edge Falling RX-XCK Edge
// 1=Falling TX-XCK Edge Rising RX-XCK Edge
//+-----------+
//| UBRRH | = 0x00
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
SFRX ( UBRRH , URSEL_L | UBRR11_L | UBRR10_L | UBRR09_L | UBRR08_L ) ;
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
// 0 . . . . . . . = 0 = select UBRRH (this) register
// n . . . . . . . 1 = select UCSRC register
// . . . . 0 0 0 0 = 0000 is part of baudrate setting, see UBRRL
//
//+-----------+
//| UBRRL | = 0xCF = 207 = 2400baud
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
SFRX ( UBRRL , UBRR07_L | UBRR06_H | UBRR05_H | UBRR04_L | UBRR03_L | UBRR02_H | UBRR01_H | UBRR00_H ) ;
//+-----------+----------+----------+----------+----------+----------+----------+----------+----------+
// 1 1 0 0 1 1 1 1 = 0xCF = 207 = 2400baud
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