📄 fusb200.h
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#ifndef _FUSB200_H
#define _FUSB200_H
#include "reg51.h"
#include "type.h"
#include "stdio.h"
sbit P0_0 = P0^0;
#define HS_MODE
//#define FS_MODE
#define BULK_TRANSFERS
//#define INT_TRANSFERS
//#define ISO_TRANSFERS
#define FUSB_REG_BASE_ADDR 0x0
typedef unsigned char FUSB_REG;
//-------------------------------------------------------
// Registers address
//-------------------------------------------------------
#define FUSB_REG_MAIN_CTL (FUSB_REG_BASE_ADDR + 0x00)
#define FUSB_REG_DEVICE_ADDR (FUSB_REG_BASE_ADDR + 0x01)
#define FUSB_REG_TEST_EP (FUSB_REG_BASE_ADDR + 0x02)
#define FUSB_REG_PHY_TMS (FUSB_REG_BASE_ADDR + 0x08)
#define FUSB_REG_CX_CSR (FUSB_REG_BASE_ADDR + 0X0B)
#define FUSB_REG_EP0_DATA (FUSB_REG_BASE_ADDR + 0x0C)
#define FUSB_REG_INT_MGRP (FUSB_REG_BASE_ADDR + 0x10)
#define FUSB_REG_INT_MSKB0 (FUSB_REG_BASE_ADDR + 0x11)
#define FUSB_REG_INT_MSKB1 (FUSB_REG_BASE_ADDR + 0x12)
#define FUSB_REG_INT_MSKB5 (FUSB_REG_BASE_ADDR + 0x16)
#define FUSB_REG_INT_MSKB7 (FUSB_REG_BASE_ADDR + 0x18)
#define FUSB_REG_INT_GROUP (FUSB_REG_BASE_ADDR + 0x20)
#define FUSB_REG_INT_SOURCE0 (FUSB_REG_BASE_ADDR + 0x21)
#define FUSB_REG_INT_SOURCE1 (FUSB_REG_BASE_ADDR + 0x22)
#define FUSB_REG_INT_SOURCE2 (FUSB_REG_BASE_ADDR + 0x23)
#define FUSB_REG_INT_SOURCE3 (FUSB_REG_BASE_ADDR + 0x24)
#define FUSB_REG_INT_SOURCE4 (FUSB_REG_BASE_ADDR + 0x25)
#define FUSB_REG_INT_SOURCE5 (FUSB_REG_BASE_ADDR + 0x26)
#define FUSB_REG_INT_SOURCE6 (FUSB_REG_BASE_ADDR + 0x27)
#define FUSB_REG_INT_SOURCE7 (FUSB_REG_BASE_ADDR + 0x28)
#define FUSB_REG_IDLE_CNT (FUSB_REG_BASE_ADDR + 0x2F)
#define FUSB_REG_EP1_MAP (FUSB_REG_BASE_ADDR + 0x30)
#define FUSB_REG_EP2_MAP (FUSB_REG_BASE_ADDR + 0x31)
#define FUSB_REG_IEP1_XPSZ_L (FUSB_REG_BASE_ADDR + 0x40)
#define FUSB_REG_IEP1_XPSZ_H (FUSB_REG_BASE_ADDR + 0x41)
#define FUSB_REG_OEP2_XPSZ_L (FUSB_REG_BASE_ADDR + 0x62)
#define FUSB_REG_OEP2_XPSZ_H (FUSB_REG_BASE_ADDR + 0x63)
#define FUSB_REG_FIFO0_MAP (FUSB_REG_BASE_ADDR + 0x80)
#define FUSB_REG_FIFO1_MAP (FUSB_REG_BASE_ADDR + 0x81)
#define FUSB_REG_FIFO2_MAP (FUSB_REG_BASE_ADDR + 0x82)
#define FUSB_REG_FIFO3_MAP (FUSB_REG_BASE_ADDR + 0x83)
#define FUSB_REG_FIFO6_MAP (FUSB_REG_BASE_ADDR + 0x86)
#define FUSB_REG_FIFO0_CFG (FUSB_REG_BASE_ADDR + 0x90)
#define FUSB_REG_FIFO1_CFG (FUSB_REG_BASE_ADDR + 0x91)
#define FUSB_REG_FIFO2_CFG (FUSB_REG_BASE_ADDR + 0x92)
#define FUSB_REG_FIFO3_CFG (FUSB_REG_BASE_ADDR + 0x93)
#define FUSB_REG_FIFO4_CFG (FUSB_REG_BASE_ADDR + 0x94)
#define FUSB_REG_FIFO6_CFG (FUSB_REG_BASE_ADDR + 0x96)
#define FUSB_REG_FIFO0_INS (FUSB_REG_BASE_ADDR + 0xA0)
#define FUSB_REG_FIFO1_INS (FUSB_REG_BASE_ADDR + 0xA1)
#define FUSB_REG_FIFO3_INS (FUSB_REG_BASE_ADDR + 0xA3)
#define FUSB_REG_FIFO0_BCNT (FUSB_REG_BASE_ADDR + 0xB0)
#define FUSB_REG_FIFO0_DP (FUSB_REG_BASE_ADDR + 0xC0)
#define FUSB_REG_FIFO1_DP (FUSB_REG_BASE_ADDR + 0xC4)
#define FUSB_REG_FIFO2_DP (FUSB_REG_BASE_ADDR + 0xC8)
#define FUSB_REG_FIFO3_DP (FUSB_REG_BASE_ADDR + 0xCC)
/* main_ctl addr:0x00*/
#define FUSB_MAIN_CTL_HS_EN (1U << 6)
#define FUSB_MAIN_CTL_CHIP_EN (1U << 5)
#define FUSB_MAIN_CTL_SFRST (1U << 4)
#define FUSB_MAIN_CTL_GOSUSP (1U << 3)
#define FUSB_MAIN_CTL_GLINT_EN (1U << 2)
#define FUSB_MAIN_CTL_CAP_RMWKUP (1U << 0)
/* interrupt_group addr:0x20 */
#define FUSB_INT_GROUP_INT_SCR7 (1U << 7)
#define FUSB_INT_GROUP_INT_SCR6 (1U << 6)
#define FUSB_INT_GROUP_INT_SCR5 (1U << 5)
#define FUSB_INT_GROUP_INT_SCR4 (1U << 4)
#define FUSB_INT_GROUP_INT_SCR3 (1U << 3)
#define FUSB_INT_GROUP_INT_SCR2 (1U << 2)
#define FUSB_INT_GROUP_INT_SCR1 (1U << 1)
#define FUSB_INT_GROUP_INT_SCR0 (1U << 0)
/* interrupt_source Byte0 addr:0x21 */
#define FUSB_INT_SOURCE0_CX_COMABT_INT (1U << 7)
#define FUSB_INT_SOURCE0_CX_COMFAIL_INT (1U << 4)
#define FUSB_INT_SOURCE0_CX_COMEND_INT (1U << 3)
#define FUSB_INT_SOURCE0_CX_OUT_INT (1U << 2)
#define FUSB_INT_SOURCE0_CX_IN_INT (1U << 1)
#define FUSB_INT_SOURCE0_CX_SETUP_INT (1U << 0)
/* interrupt_source Byte7 addr:0x28 */
#define FUSB_INT_SOURCE7_RX0BTYE_INT (1U << 7)
#define FUSB_INT_SOURCE7_TX0BTYE_INT (1U << 6)
#define FUSB_INT_SOURCE7_ISO_SEQ_ABORT_INT (1U << 5)
#define FUSB_INT_SOURCE7_ISO_SEQ_ERR_INT (1U << 4)
#define FUSB_INT_SOURCE7_RESM_INT (1U << 3)
#define FUSB_INT_SOURCE7_SUSP_INT (1U << 2)
#define FUSB_INT_SOURCE7_USBRST_INT (1U << 1)
#define FUSB_EP_COUNT 2U
#define FUSB_EP15_ID 15U
#define FUSB_EP14_ID 14U
#define FUSB_EP13_ID 13U
#define FUSB_EP12_ID 12U
#define FUSB_EP11_ID 11U
#define FUSB_EP10_ID 10U
#define FUSB_EP9_ID 9U
#define FUSB_EP8_ID 8U
#define FUSB_EP7_ID 7U
#define FUSB_EP6_ID 6U
#define FUSB_EP5_ID 5U
#define FUSB_EP4_ID 4U
#define FUSB_EP3_ID 3U
#define FUSB_EP2_ID 2U
#define FUSB_EP1_ID 1U
#define FUSB_EP0_ID 0U
#define FUSB_EP_IN 1U
#define FUSB_EP_OUT 0U
#define FUSB_EP0_SIZE 64U // fixed
#ifdef HS_MODE
#define FUSB_EP1_SIZE 512U
#define FUSB_EP2_SIZE 512U
#else
#define FUSB_EP1_SIZE 64U
#define FUSB_EP2_SIZE 64U
#endif
// the input EP this design used, if EPn is used, the nth bit of EP_IN_USE is 1.
#define EP_IN_USE (1U << FUSB_EP0_ID | 1U << FUSB_EP1_ID)
//#define EP_IN_USE (1U << FUSB_EP0_ID | 1U << FUSB_EP2_ID)
// numbers of IN endpoints
// Legal values are 1 - 16 (this value includes EP0)
#define C_NUM_EPI 2
// the output EP this design used, if EPn is used, the nth bit of EP_OUT_USE is 1.
#define EP_OUT_USE (1U << FUSB_EP2_ID)
//#define EP_OUT_USE (1U << FUSB_EP2_ID | 1U << FUSB_EP3_ID)
// numbers of IN endpoints
// Legal values are 1 - 16 (this value includes EP0)
#define C_NUM_EPO 2
//enum ep0_state_m {IDLE, TX, RX};
//enum device_states_m {ATTACHED, POWERED, DEFAULT, ADDRESS, CONFIGURED, SUSPENDED};
struct dev_req_s{
u8 bmRequestType;
u8 bRequest;
u16 wValue;
u16 wIndex;
u16 wLength;
};
//-----------------------------------------------------------
// DataTypes
//-----------------------------------------------------------
struct DEVICEDSCR{ // Device Descriptor
u8 length; // Descriptor length ( = sizeof(DEVICEDSCR) )
u8 type; // Decriptor type (Device = 1)
u8 spec_ver_minor; // Specification Version (BCD) minor
u8 spec_ver_major; // Specification Version (BCD) major
u8 dev_class; // Device class
u8 sub_class; // Device sub-class
u8 protocol; // Device sub-sub-class
u8 max_packet; // Maximum packet size
u16 vendor_id; // Vendor ID
u16 product_id; // Product ID
u16 version_id; // Product version ID
u8 mfg_str; // Manufacturer string index
u8 prod_str; // Product string index
u8 serialnum_str; // Serial number string index
u8 configs; // Number of configurations
};
//#define MSG_SIZE 1000
//typedef struct _FUSBHSFC {
// enum ep0_state_m ep0_state;
//
// dev_req_t dev_req;
//
// enum device_states_m device_state;
//
// u16 in_fifo_size[FUSB_EP_COUNT];
// u16 out_fifo_size[FUSB_EP_COUNT];
//
// //u8 msg[MSG_SIZE];
// u8 msg_len;
//
// u8 currentConfiguration;
//
// u8 reset;
//}FUSBHSFC, *pFUSBHSFC;
//-----------------------------------------------------------------------------
// Globals
//-----------------------------------------------------------------------------
extern struct dev_req_s dev_req;
extern struct DEVICEDSCR DeviceDscr;
//-----------------------------------------------------------------------------
// Function Prototypes
//-----------------------------------------------------------------------------
extern void init_m8051ew();
extern void init_fusb();
extern void init_interrupt();
extern void irq_int();
extern void delay();
extern void ep0_int_service();
extern void ep1_int_service();
extern void ep2_int_service();
#endif //#ifndef _FUSB200_H⌨️ 快捷键说明
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