📄 isd51.lst
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A51 MACRO ASSEMBLER ISD51 08/18/2006 11:05:50 PAGE 5
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313
314
315 ;------------------------------------------------------------------------------
316 ;----------------- !!! Do not modify code sections below !!! ------------------
317 ;------------------------------------------------------------------------------
318
319 NAME ISD51_CONFIGURATION
320
321
322 SBYTE MACRO ; Transmit Byte in ACC via serial UART
A51 MACRO ASSEMBLER ISD51 08/18/2006 11:05:50 PAGE 6
323 JNB_TI $
324 CLR_TI
325 WR_SBUF ; MOV SBUF,A
326 ENDM
327
328 RBYTE MACRO ; Read one Byte from serial UART to ACC
329 RD_SBUF ; MOV A,SBUF
330 CLR_RI
331 ENDM
332
333 GBYTE MACRO ; Receive one Character from 8051 Serial Interface
334 JNB_RI $
335 RBYTE
336 ENDM
337
338
339
0080 340 sfr P0 = 0x80;
0090 341 sfr P1 = 0x90;
00A0 342 sfr P2 = 0xA0;
00B0 343 sfr P3 = 0xB0;
00D0 344 sfr PSW = 0xD0;
00E0 345 sfr ACC = 0xE0;
00F0 346 sfr B = 0xF0;
0081 347 sfr SP = 0x81;
0082 348 sfr DPL = 0x82;
0083 349 sfr DPH = 0x83;
008E 350 sfr AUXR = 0x8E;
00E4 351 sfr PH_FMCON = 0xE4; // for Philips LPC900 devices
00E6 352 sfr PH_FMADRL = 0xE6; // for Philips LPC900 devices
353
354
00FF 355 ?ISD?RAMTOP EQU 0x100-1
0000 356 ?ISD?CMP_S EQU 0x0
7FFF 357 ?ISD?CMP_E EQU 0x7FFF
358
359 EXTRN NUMBER (?ISD?CORE)
360
361 PUBLIC ?ISD?RAMTOP
362 PUBLIC ?ISD?RESTART
363 PUBLIC ?ISD?CMDLOOP
364 PUBLIC ?ISD?GETBYTE
365 PUBLIC ?ISD?SENDBYTE
366 PUBLIC ?ISD?READSFR00
367 PUBLIC ?ISD?READSFR01
368 PUBLIC ?ISD?READSFR02
369 PUBLIC ?ISD?READSFR03
370 PUBLIC ?ISD?READSFR04
371 PUBLIC ?ISD?READSFR05
372 PUBLIC ?ISD?READSFR06
373 PUBLIC ?ISD?READSFR07
374 PUBLIC ?ISD?READSFR08
375 PUBLIC ?ISD?READSFR09
376 PUBLIC ?ISD?READSFR10
377 PUBLIC ?ISD?READSFR11
378 PUBLIC ?ISD?READSFR12
379 PUBLIC ?ISD?READSFR13
380 PUBLIC ?ISD?READSFR14
381 PUBLIC ?ISD?READSFR15
382 PUBLIC ?ISD?READSFR16
383 PUBLIC ?ISD?READSFR17
384 PUBLIC ?ISD?READSFR18
385 PUBLIC ?ISD?WRITESFR00
386 PUBLIC ?ISD?WRITESFR01
387 PUBLIC ?ISD?WRITESFR02
388 PUBLIC ?ISD?WRITESFR03
A51 MACRO ASSEMBLER ISD51 08/18/2006 11:05:50 PAGE 7
389
393 PUBLIC ?ISD?VERSION
394 PUBLIC ?ISD?CMP_S
395 PUBLIC ?ISD?CMP_E
396 PUBLIC __isd_init
397
398
399 PUBLIC ?ISD?CBLK_SIZE ; block size for FLASH IAP Routine
400
0080 401 ?ISD?CBLK_SIZE EQU 128
0010 402 CBLK EQU 10H ; Start address for FLASH buffer
403
00CD 404 ?ISD?VERSION EQU 205 ; Version 2.05
405
406
407 ?BI?ISD51 SEGMENT BIT
---- 408 RSEG ?BI?ISD51
0000 409 SaveEAI: DBIT 1 ; Save TI AUX Interrupt Enable bit
410
411
412
413 ?PR?ISD51 SEGMENT CODE INBLOCK
414
---- 415 CSEG AT SINTRVEC ; Serial Interrupt
0023 020000 F 416 LJMP SerialInterrupt
417
418
419
A51 MACRO ASSEMBLER ISD51 08/18/2006 11:05:50 PAGE 8
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