📄 atj2085_ports.h
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#define MFP_GPOA_SELECT_REG (0xee) /* default 0x01 */
/* Bit 7-5 */
#define MFP_SELECT_MASK 0xe0
#define MFP_SELECT_F4 0x60
#define MFP_SELECT_F3 0x40
#define MFP_SELECT_F2 0x20
#define MFP_SELECT_F1 0x00
/* Bit 4-3 */
#define MFP_SELECT_CS0S 0x10
#define GPOA2_ENABLE 0x08
/* Bit 2-0 */
#define GPOA2_OUTPUT_2 0x04
#define GPOA2_OUTPUT_1 0x02
#define GPOA2_OUTPUT_0 0x01
#define GPIOB_CONFIG_REG (0xef) /* default 0x00 */
/* Bit 7 */
#define GPIOB_CONFIG_RESERVED1 0x80 /* DO NOT WRITE WITH 1 */
/* Bit 6-4 GPIO B6-4 enable or KEY02-KEY00 select*/
#define GPIOB_CONFIG_B6_INV 0x40
#define GPIOB_CONFIG_B5_INV 0x20
#define GPIOB_CONFIG_B4_INV 0x10
/* Bit 3 */
#define GPIOB_CONFIG_RESERVED2 0x08 /* DO NOT WRITE WITH 1 */
/* Bit 2-0 */
#define GPIOB_CONFIG_B2_INV 0x04
#define GPIOB_CONFIG_B1_INV 0x02
#define GPIOB_CONFIG_B0_INV 0x01
#define GPIOB_OUTPUT_ENABLE_REG (0xf0) /* default 0x00 */
/* Bit 7 */
#define GPIOB_OUTPUT_RESERVED1 0x80 /* DO NOT WRITE WITH 1 */
/* Bit 6-4 GPIOB Output Enable */
#define GPIOB_OUTPUT_ENABLE_6 0x40
#define GPIOB_OUTPUT_ENABLE_5 0x20
#define GPIOB_OUTPUT_ENABLE_4 0x10
/* Bit 3 */
#define GPIOB_OUTPUT_RESERVED2 0x08 /* DO NOT WRITE WITH 1 */
/* Bit 2-0 GPIOB Output Enable */
#define GPIOB_OUTPUT_ENABLE_2 0x04
#define GPIOB_OUTPUT_ENABLE_1 0x02
#define GPIOB_OUTPUT_ENABLE_0 0x01
#define GPIOB_OUTPUT_ENABLE_ALL (GPIOB_OUTPUT_ENABLE_0 | GPIOB_OUTPUT_ENABLE_1 | GPIOB_OUTPUT_ENABLE_2 | GPIOB_OUTPUT_ENABLE_4 | GPIOB_OUTPUT_ENABLE_5 | GPIOB_OUTPUT_ENABLE_6)
#define GPIOB_INPUT_ENABLE_REG (0xf1) /* default 0x00 */
/* Bit 7 */
#define GPIOB_INPUT_RESERVED1 0x80 /* DO NOT WRITE WITH 1 */
/* Bit 6-4 GPIOB Input Enable */
#define GPIOB_INPUT_ENABLE_6 0x40
#define GPIOB_INPUT_ENABLE_5 0x20
#define GPIOB_INPUT_ENABLE_4 0x10
/* Bit 3 */
#define GPIOB_INPUT_RESERVED2 0x08 /* DO NOT WRITE WITH 1 */
/* Bit 2-0 GPIOB Input Enable */
#define GPIOB_INPUT_ENABLE_2 0x04
#define GPIOB_INPUT_ENABLE_1 0x02
#define GPIOB_INPUT_ENABLE_0 0x01
#define GPIOB_INPUT_ENABLE_ALL (GPIOB_INPUT_ENABLE_0 | GPIOB_INPUT_ENABLE_1 |GPIOB_INPUT_ENABLE_2 | GPIOB_INPUT_ENABLE_4 | GPIOB_INPUT_ENABLE_5 | GPIOB_INPUT_ENABLE_6)
#define GPIOB_DATA_REG (0xf2) /* default 0x00 */
/* Bit 7-0 Data input output register */
#define GPIOB_DATA_RESERVED1 0x80 /* DO NOT WRITE WITH 1 */
/* Bit 6-4 */
#define GPIOB_DATA_BIT_6 0x40
#define GPIOB_DATA_BIT_5 0x20
#define GPIOB_DATA_BIT_4 0x10
/* Bit 3 */
#define GPIOB_DATA_RESERVED2 0x08 /* DO NOT WRITE WITH 1 */
/* Bit 2-0 */
#define GPIOB_DATA_BIT_2 0x04
#define GPIOB_DATA_BIT_1 0x02
#define GPIOB_DATA_BIT_0 0x01
#define GPIOB_DATA_BIT_MASK (GPIOB_DATA_BIT_0 | GPIOB_DATA_BIT_1 | GPIOB_DATA_BIT_2 | GPIOB_DATA_BIT_4 | GPIOB_DATA_BIT_5 | GPIOB_DATA_BIT_6)
#define GPIOC_ENABLE_REG (0xf3) /* default 0x07 */
/* Bit 7 */
#define GPIOC_ENABLE_RESERVED1 0x80 /* DO NOT WRITE WITH 1 */
/* Bit 6-4 Input Enable*/
#define GPIOC_OUTPUT_ENABLE_2 0x40
#define GPIOC_OUTPUT_ENABLE_1 0x20
#define GPIOC_OUTPUT_ENABLE_0 0x10
/* Bit 3 */
#define GPIOC_ENABLE_RESERVED2 0x08 /* DO NOT WRITE WITH 1 */
/* Bit 2-0 Output Enable */
#define GPIOC_INPUT_ENABLE_2 0x04
#define GPIOC_INPUT_ENABLE_1 0x02
#define GPIOC_INPUT_ENABLE_0 0x01
#define GPIOC_DATA_REG (0xf4) /* default 0x03 */
/* Bit 7-3 Reserved */
#define GPIOC_DATA_RESERVED1 0x80 /* DO NOT WRITE WITH 1 */
#define GPIOC_DATA_RESERVED2 0x40 /* DO NOT WRITE WITH 1 */
#define GPIOC_DATA_RESERVED3 0x20 /* DO NOT WRITE WITH 1 */
#define GPIOC_DATA_RESERVED4 0x10 /* DO NOT WRITE WITH 1 */
#define GPIOC_DATA_RESERVED5 0x08 /* DO NOT WRITE WITH 1 */
/* Bit 2-0 */
#define GPIOC_DATA_BIT_2 0x04
#define GPIOC_DATA_BIT_1 0x02
#define GPIOC_DATA_BIT_0 0x01
#define GPIOC_DATA_BIT_MASK (GPIOC_DATA_BIT_0 | GPIOC_DATA_BIT_1 | GPIOC_DATA_BIT_2)
/* Used in BRECF644.BIN */
#define JOHNDOE1 (0xf5)
#define JOHNDOE2 (0xf7)
#define JOHNDOE3 (0xf8)
#define JOHNDOE4 (0xfa)
#define GPIOG_ENABLE_REG (0xfe) /* default 0x00 */
/* Bit 7-5 Reserved */
#define GPIOG_ENABLE_RESERVED1 0x80 /* DO NOT WRITE WITH 1 */
#define GPIOG_ENABLE_RESERVED2 0x40 /* DO NOT WRITE WITH 1 */
#define GPIOG_ENABLE_RESERVED3 0x20 /* DO NOT WRITE WITH 1 */
/* Bit 4 Input Enable*/
#define GPIOG_OUTPUT_ENABLE_0 0x10
/* Bit 3-1 */
#define GPIOG_ENABLE_RESERVED4 0x08 /* DO NOT WRITE WITH 1 */
#define GPIOG_ENABLE_RESERVED5 0x04 /* DO NOT WRITE WITH 1 */
#define GPIOG_ENABLE_RESERVED6 0x02 /* DO NOT WRITE WITH 1 */
/* Bit 0 Output Enable */
#define GPIOG_INPUT_ENABLE_0 0x01
#define GPIOG_DATA_REG (0xff) /* default 0x00 */
/* Bit 7-1 Reserved */
#define GPIOG_DATA_RESERVED1 0x80 /* DO NOT WRITE WITH 1 */
#define GPIOG_DATA_RESERVED2 0x40 /* DO NOT WRITE WITH 1 */
#define GPIOG_DATA_RESERVED3 0x20 /* DO NOT WRITE WITH 1 */
#define GPIOG_DATA_RESERVED4 0x10 /* DO NOT WRITE WITH 1 */
#define GPIOG_DATA_RESERVED5 0x08 /* DO NOT WRITE WITH 1 */
#define GPIOG_DATA_RESERVED6 0x04 /* DO NOT WRITE WITH 1 */
#define GPIOG_DATA_RESERVED7 0x02 /* DO NOT WRITE WITH 1 */
/* Bit 0 */
#define GPIOG_DATA_BIT_0 0x01
#define GPIOG_DATA_BIT_MASK (GPIOG_DATA_BIT_0)
/*-----------------------------------------------------------------------------*/
/*RTC/LOSC/WATCHDOG */
/*-----------------------------------------------------------------------------*/
#define RTC_CONTROL_REG (0x43) /* default 0x04 */
/* Bit 7-0 */
#define RTC_CONTROL_ALARM_ENABLE 0x80
#define RTC_CONTROL_TIMER_ENABLE 0x40
#define RTC_CONTROL_IRQ2HZEN_ENABLE 0x20
#define RTC_CONTROL_CLEAR_RTC_COUNT 0x10
#define RTC_CONTROL_LOAD_RTC_COUNT 0x08
#define RTC_CONTROL_RESERVED1 0x04
#define RTC_CONTROL_RESERVED2 0x02
#define RTC_CONTROL_OVERFLOW 0x01
#define RTC_IRQSTATUS_REG (0x44) /* default 0x00 */
/* Bit 7-0 */
#define RTC_IRQSTATUS_XTAL_OSC_ENABLE 0x80
#define RTC_IRQSTATUS_CLK_SOURCE 0x40
#define RTC_IRQSTATUS_RESERVED1 0x20
#define RTC_IRQSTATUS_RESERVED2 0x10
#define RTC_IRQSTATUS_RESERVED3 0x08
#define RTC_IRQSTATUS_RTC_ALARM_IRQ 0x04
#define RTC_IRQSTATUS_RTC_TIMER_IRQ 0x02
#define RTC_IRQSTATUS_2HZ_IRQ 0x01
#define RTC_TIME_LO_REG (0x45)
#define RTC_TIME_MI_REG (0x46)
#define RTC_TIME_HI_REG (0x47)
#define RTC_ALARM_LO_REG (0x48) /* default 0x22 */
#define RTC_ALARM_MI_REG (0x49) /* default 0x22 */
#define RTC_ALARM_HI_REG (0x4a) /* default 0x22 */
#define LOSC_DIV_LO_REG (0x4b) /* default 0x22 */
#define LOSC_DIV_MI_REG (0x4c) /* default 0x22 */
#define LOSC_DIV_HI_REG (0x4d) /* default 0x22 */
#define WATCHDOG_REG (0x4e) /* default 0x22 */
/* Bit 7 */
#define WATCHDOG_ENABLE 0x80
/* Bit 6-4 Watch dog timer select */
#define WATCHDOG_MASK 0x70
#define WATCHDOG_180S 0x70
#define WATCHDOG_90S 0x60
#define WATCHDOG_45S 0x50
#define WATCHDOG_22_2S 0x40
#define WATCHDOG_5_6S 0x30
#define WATCHDOG_1_4S 0x20
#define WATCHDOG_0_352S 0x10
#define WATCHDOG_0_176S 0x00
/* Bit 3-0 */
#define WATCHDOG_RESET 0x08
#define WATCHDOG_RESERVED1 0x04
#define WATCHDOG_RESERVED2 0x02
#define WATCHDOG_RESERVED3 0x01
/*-----------------------------------------------------------------------------*/
/*HOSC/PLL */
/*-----------------------------------------------------------------------------*/
#define HFC_CONTROL_REG 0x40 /* def=04h */
#define PLL_PERFORMANCE_REG 0x41 /* def=55h */
#define PLL_CONTROL_REG (0x42)
/*-----------------------------------------------------------------------------*/
/*PMU/DC-DC */
/*-----------------------------------------------------------------------------*/
#define VOLTAGE_CONTROL_REG 0x3f
/* def=0ech (DCDC_CONTROL_REG) */
#define DCDC_CONTROL_REG 0x4f
/* def=0101b */
#define BATTERY_MON_REG 0xd0
/* def=28h */
/* define POWER_CONTROL_REG 0dfh */
#define POWER_CONTROL_REG 0xdf
/*-----------------------------------------------------------------------------*/
/*ADC/DAC/HEADPHONE */
/*-----------------------------------------------------------------------------*/
#define DAC_CONTROL_REG1 0x80 /* def=03h */
#define DAC_RATECTRL_REG 0x81 /* write only */
#define DAC_PCMOUT_LO_REG 0x88 /* write only */
#define DAC_PCMOUT_MI_REG 0x89 /* write only */
#define DAC_PCMOUT_HI_REG 0x8a /* def=15h */
#define FIFO_STATUS_REG 0x8b /* def=07h */
#define DAC_CONTROL_REG2 0x91
/*-----------------------------------------------------------------------------*/
/*DAC ANALOG */
/*-----------------------------------------------------------------------------*/
/* def=40h */
#define DACA_VOLCTRL_REG 0x9e
#define DACA_BLKCTRL_REG 0xdd
/*-----------------------------------------------------------------------------*/
/*ADC */
/*-----------------------------------------------------------------------------*/
#define ADC_DATA_REG 0x9a /* read only */
#define SARADC_CONTROL_REG 0xd1 /* def=04h */
#define ADC_PERFORMANCE_REG 0xd3 /* def=03h */
#define ADC_MODULEPERF_REG 0x9f /* def=5dh */
#define ADC_CONTROL_REG1 0xd4 /* def=05h */
#define ADC_CONTROL_REG2 0xd5
#define ADC_GAINCTRL_REG 0xd6 /* def=55h */
#define ADC_FIFOCTRL_REG 0xd7
#define ADC_BUSCTRL_REG 0x9b
#define LRADC_DATA_REG 0xd8 /* read only */
#define SARADC_IRQCTRL_REG 0xde /* write (def=80h) */
#define SARADC_IRQSTAT_REG 0xde /* read (def=80h) */
#endif /*__ATJ2085_PORTS_H__*/
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