atj2085_ports.h

s1mp3 sdk, action mp3 develop tool kit!

#define USB_STATUS_CONTROL_REG     (0x50)
/* Bit 7-0 */
#define USB_CONTROL_SUSPEND         0x80
#define USB_STATUS_POWER            0x40
#define USB_STATUS_DPLUS_LEVEL      0x20
#define USB_STATUS_DMINUS_LEVEL     0x10
#define USB_STATUS_BUS_ACTIVE       0x08
#define USB_CONTROL_FORCE_DRIVE     0x04
#define USB_CONTROL_FORCE_DPLUS     0x02
#define USB_CONTROL_FORCE_DMINUS    0x01

#define USB_DEVADDR_REG     	   (0x51)
/* Bit 7 */
#define USB_DEVADDR_ENABLE     	    0x80
/* Bit 6-0 */
#define USB_DEVADDR_MASK     	    0x7F

#define USB_INT_STATUS_REG  	   (0x52)
/* Bit 7-4 */
#define USB_INT_BUS_RESET  	        0x80
#define USB_INT_BUS_CON_DISC        0x40
#define USB_INT_EP0_SETUP  	        0x20
#define USB_INT_WAKEUP_IRQ 	        0x10
/* Bit 3-0 Reserved */

#define USB_EP_STATUS_REG   	   (0x53)
/* Bit 7-0 */
#define USB_EP_ENDPOINT3_OUT        0x80
#define USB_EP_ENDPOINT3_IN         0x40
#define USB_EP_ENDPOINT2_OUT        0x20
#define USB_EP_ENDPOINT2_IN         0x10
#define USB_EP_ENDPOINT1_OUT        0x08
#define USB_EP_ENDPOINT1_IN         0x04
#define USB_EP_CONTROL_WRITE        0x02
#define USB_EP_CONTROL_READ         0x01

#define USB_FRAME_HI_REG    	   (0x54)
/* Bit 7 */
#define USB_FRAME_HI_CRC5_CHECK     0x80
/* Bit 6-3 Reserved */
/* Bit 2-0 */
#define USB_FRAME_HI_MASK           0x07

#define USB_FRAME_LO_REG    	   (0x55)
/* Bit 7-0 */

#define USB_RESERVED56_REG  	   (0x56)

#define USB_SETUP_STATUS_REG	   (0x57)
/* Bit 7-4 */
#define USB_SETUP_DATA_TOGGLE	    0x80
#define USB_SETUP_DATA_VALID  	    0x40
#define USB_SETUP_IGNORE_TOKEN	    0x20
#define USB_SETUP_ACK_TX    	    0x10
/* Bit 3-0 */
#define USB_SETUP_DATA_COUNT_MASK   0x0F

#define USB_SETUP_DATA0_REG 	   (0x58)
#define USB_SETUP_DATA1_REG 	   (0x59)
#define USB_SETUP_DATA2_REG 	   (0x5a)
#define USB_SETUP_DATA3_REG 	   (0x5b)
#define USB_SETUP_DATA4_REG 	   (0x5c)
#define USB_SETUP_DATA5_REG 	   (0x5d)
#define USB_SETUP_DATA6_REG 	   (0x5e)
#define USB_SETUP_DATA7_REG 	   (0x5f)

#define USB_EPI_REG         	   (0x60)
/* Bit 7-3 reserved */
/* Bit 2-0 */
#define USB_EPI_ENDPOINT3_OUT       0x07
#define USB_EPI_ENDPOINT3_IN        0x06
#define USB_EPI_ENDPOINT2_OUT       0x05
#define USB_EPI_ENDPOINT2_IN        0x04
#define USB_EPI_ENDPOINT1_OUT       0x03
#define USB_EPI_ENDPOINT1_IN        0x02
#define USB_EPI_CONTROL_WRITE       0x01
#define USB_EPI_CONTROL_READ        0x00

#define USB_EPI_MODE_REG    	   (0x61)
/* Bit 7-3 (2) reserved */
/* Bit 2 if EP1IN or EP2IN or EP3IN */
#define USB_EPI_MODE_ISONBR         0x04
/* Bit 1 if EP1IN or EP2IN or EP3IN or EP1OUT or EP2OUT or EP3OUT */
#define USB_EPI_MODE_ISO            0x02
/* Bit 1 if EPI=0 or 1*/
#define USB_EPI_MODE_COMPLETE       0x02
/* Bit 0 Common */
#define USB_EPI_MODE_STALL          0x01

#define USB_EPI_START_ADDR_HI_REG  (0x62)
#define USB_EPI_START_ADDR_LO_REG  (0x63)

#define USB_EPI_CNTR_HI_REG 	   (0x64)
#define USB_EPI_CNTR_LO_REG 	   (0x65)

#define USB_EPI_MPS_REG     	   (0x66)
/* Bit 7-6 */
#define USB_EPI_MPS_SPR             0x80    /* Read  */
#define USB_EPI_MPS_FORCE_TOGGLE    0x80    /* Write */
#define USB_EPI_MPS_NEW_TOGGLE      0x40    /* Read  */
#define USB_EPI_MPS_CURRENT_TOGGLE  0x40    /* Write */
/* Bit 5-0 Maximum Packet Size */
#define USB_EPI_MPS_MASK            0x3F


#define USB_RESERVED67_REG  	   (0x67)

#define USB_EPI_EPSBR_REG   	   (0x68)
/* Bit 7-0 */
#define USB_EPI_EPSBR_EP3_OUT       0x80
#define USB_EPI_EPSBR_EP3_IN        0x40
#define USB_EPI_EPSBR_EP2_OUT       0x20
#define USB_EPI_EPSBR_EP2_IN        0x10
#define USB_EPI_EPSBR_EP1_OUT       0x08
#define USB_EPI_EPSBR_EP1_IN        0x04
#define USB_EPI_EPSBR_CTL_WRITE     0x02
#define USB_EPI_EPSBR_CTL_READ      0x01

#define USB_EPI_EPSNS_REG   	   (0x69)
/* Bit 7-0 */
#define USB_EPI_EPSNS_EP3_OUT_NAK   0x80
#define USB_EPI_EPSNS_EP3_IN_NAK    0x40
#define USB_EPI_EPSNS_EP2_OUT_NAK   0x20
#define USB_EPI_EPSNS_EP2_IN_NAK    0x10
#define USB_EPI_EPSNS_EP1_OUT_NAK   0x08
#define USB_EPI_EPSNS_EP1_IN_NAK    0x04
#define USB_EPI_EPSNS_CTL_WRITE     0x02
#define USB_EPI_EPSNS_CTL_READ      0x01

#define USB_EPI_EPSST_REG   	   (0x6a)
/* Bit 7-0 */
#define USB_EPI_EPSST_EP3_OUT_STALL 0x80
#define USB_EPI_EPSST_EP3_IN_STALL  0x40
#define USB_EPI_EPSST_EP2_OUT_STALL 0x20
#define USB_EPI_EPSST_EP2_IN_STALL  0x10
#define USB_EPI_EPSST_EP1_OUT_STALL 0x08
#define USB_EPI_EPSST_EP1_IN_STALL  0x04
#define USB_EPI_EPSST_CTL_WRITE     0x02
#define USB_EPI_EPSST_CTL_READ      0x01

#define USB_IRQSTATUS_REG     	   (0x6b)

#define USB_JOHNDOE1_REG     	   (0x6c)
#define USB_JOHNDOE2_REG     	   (0x6e)
#define USB_JOHNDOE3_REG     	   (0x6f)

#define USB_RESERVED76_REG  	   (0x76)

/*-----------------------------------------------------------------------------*/
/*(SAMSUNG) NAND FLASH SMC																										 */
/*-----------------------------------------------------------------------------*/
#define NAND_ENABLE_REG    		 		   (0x28)		/* default 0x00 */
/* Bit 7-4 reserved */
/* Bit 3-0 */                 	
#define NAND_ENABLE_CE3_INV		 			0x08
#define NAND_ENABLE_CE2_INV		 			0x04
#define NAND_ENABLE_CE1_INV		 			0x02
#define NAND_ENABLE_STATE_MACHINE		    0x01

#define NAND_CEMODE_REG    		 		   (0x29)		/* default 0x00 */
/* Bit 7-4 reserved */
/* Bit 3-0 Set new mode or old mode for banks */
#define NAND_CE_NEW_MODE_CE3	 			0x08
#define NAND_CE_NEW_MODE_CE2	 			0x04
#define NAND_CE_NEW_MODE_CE1	 			0x02
#define NAND_CEMODE_FLASH_TYPE			    0x01

#define NAND_CMD_REG       				   (0x2a)
#define NAND_CA_REG        				   (0x2b)
#define NAND_RA_REG        				   (0x2c)
#define NAND_BA_REG1       				   (0x2d)
#define NAND_BA_REG2       				   (0xec)
#define NAND_ECCCTRL_REG   				   (0xcc)
#define NAND_ECC_REG0      				   (0xcd)
#define NAND_ECC_REG1      				   (0xce)
#define NAND_ECC_REG2      				   (0xcf)

/*-----------------------------------------------------------------------------*/
/*I2C INTERFACE																																 */
/*-----------------------------------------------------------------------------*/
#define I2C_CONTROL_REG      				(0x7a)      /* default 0x00 */
/* Bit 7-4 */
#define I2C_CONTROL_ENABLE				0x80
#define I2C_CONTROL_FAST_ENABLE				0x40
#define I2C_CONTROL_IRQ_ENABLE  			0x20
#define I2C_CONTROL_SLAVE				0x10
/* Bit 3-2 Generate bus control in master mode */
#define I2C_CONTROL_REPEAT_START			0x0C
#define I2C_CONTROL_GENERATE_STOP			0x04
#define I2C_CONTROL_GENERATE_START			0x08
#define I2C_CONTROL_GENERATE_NONE			0x00
/* Bit 1-0 */
#define I2C_CONTROL_RELEASE_CLOCK_DATA	            0x02
#define I2C_CONTROL_ACK					0x01

#define I2C_STATUS_REG       				(0x7b)      /* default 0x00 */
/* Bit 7-0 */
#define I2C_STATUS_BUFFER				0x80
#define I2C_STATUS_STOP_BIT 				0x40
#define I2C_STATUS_START_BIT      			0x20
#define I2C_STATUS_READ_WRITE				0x10
#define I2C_STATUS_DATA_ADDRESS      			0x08
#define I2C_STATUS_IRQ_PENDING				0x04
#define I2C_STATUS_WRITE_COLLISION  	            0x02
#define I2C_STATUS_OVERFLOW				0x01

#define I2C_ADDR_REG         			        0x71
/* Bit 7-1 I2C Slave Address */
#define I2C_ADDR_SLAVE_ADDRESS_MASK                 0xfe
/* Bit 0 */
#define I2C_ADDR_READ_WRITE_CONTROL                 0x01

#define I2C_DATA_REG         				(0x7c)
/* Bit 7-0 Data/Address */

#define JOHNDOE5       				(0x7d)

/*-----------------------------------------------------------------------------*/
/*UART INTERFACE																																 */
/*-----------------------------------------------------------------------------*/
#define UART_CONTROL_REG      				(0x9d)

/*-----------------------------------------------------------------------------*/
/*KEY SCAN INTERFACE																													 */
/*-----------------------------------------------------------------------------*/
#define KEYSCAN_DATA_REG                           (0xc0)      /* default 0xXX */
/* Bit 7-0 KeyScan Register 12Bytes to read a write will reset */

#define KEYSCAN_CTRL_REG                           (0xc1)      /* default 0x00 */
/* Bit 7 */
#define KEYSCAN_CTRL_ENABLE                         0x80
/* Bit 6-5 */
#define KEYSCAN_CTRL_DEBOUNCE_MASK                  0x60
#define KEYSCAN_CTRL_DEBOUNCE_320                   0x60
#define KEYSCAN_CTRL_DEBOUNCE_160                   0x40
#define KEYSCAN_CTRL_DEBOUNCE_80                    0x20
#define KEYSCAN_CTRL_DEBOUNCE_40                    0x00
/* Bit 4-0*/
#define KEYSCAN_CTRL_RESERVED1                      0x10
#define KEYSCAN_CTRL_RESERVED2                      0x08
#define KEYSCAN_CTRL_MASK_KEYIN2                    0x04
#define KEYSCAN_CTRL_MASK_KEYIN1                    0x02
#define KEYSCAN_CTRL_MASK_KEYIN0                    0x01

/*-----------------------------------------------------------------------------*/
/*GPIO AND MULTI FUNCTION CONFIGURATION										   */
/*-----------------------------------------------------------------------------*/