atj2085_ports.h

s1mp3 sdk, action mp3 develop tool kit!

#ifndef __ATJ2085_PORTS_H__
#define __ATJ2085_PORTS_H__

/*-----------------------------------------------------------------------------*/
/*MCU Clock Control Registers												   */
/*-----------------------------------------------------------------------------*/
#define MCU_CLKCTRL_REG1     	       (0x00)			/* default 0x00 */
/* Bit 7-6 Wait state for external memory access */
#define MCU_EXT_MEM_WS_0			    0x00
#define MCU_EXT_MEM_WS_1			    0x40
#define MCU_EXT_MEM_WS_2			    0x80
#define MCU_EXT_MEM_WS_3			    0xC0
/* Bit 5 reserved */
#define MCU_CLK_RES				0x20
/* Bit 4 MCU clock source select */
#define MCU_CLK_SRC_SEL				    0x10
/* Bit 3-0 MCU Clock division control */
#define MCU_CLK_DIV_NONE			    0x0
#define MCU_CLK_DIV_1 				    0x1
#define MCU_CLK_DIV_4 				    0x2
#define MCU_CLK_DIV_8 				    0x3
#define MCU_CLK_DIV_16 				    0x4
#define MCU_CLK_DIV_32 				    0x5
#define MCU_CLK_DIV_64				    0x6
#define MCU_CLK_DIV_128 			    0x7
#define MCU_CLK_DIV_256				    0x8
#define MCU_CLK_DIV_512				    0x9
#define MCU_CLK_DIV_1024			    0xA
#define MCU_CLK_DIV_DC 				    0xB
/*#define MCU_CLK_DIV_256				0xC*/
/*#define MCU_CLK_DIV_512				0xD*/
/*#define MCU_CLK_DIV_1024			    0xE*/
/*#define MCU_CLK_DIV_DC 				0xF*/

#define WHOKNOWSWHATTHISIS             (0x70)
/* Bit 7-6 */

#define B1_2_MEMMAP_REG        	       (0x70)
/* Bit 5-4 */
#define B1_2_MEMMAP_B1_B2               0x30
#define B1_2_MEMMAP_B1                  0x20
#define B1_2_MEMMAP_B2                  0x10
#define B1_2_MEMMAP_NONE                0x00

#define MCU_CLKCTRL_REG     	       (0x70)
/* Bit 3 */
#define MCU_CLKCTRL_PLL                 0x08

#define DMA_CLKCTRL_REG      	       (0x70)
/* Bit 2-0 */

/*-----------------------------------------------------------------------------*/
/* External Memory Page Control Registers 									   */
/*-----------------------------------------------------------------------------*/
#define EM_PAGE_LO_REG       	       (0x01)			/* default 0x00 */
/* Bit 7-0 extended page address bits for EMA 22-15*/

#define EM_PAGE_HI_REG                 (0x02)
/* Bit 7-6 reserved*/
/* Bit 5-0 extended page address bits for EMA 28-26 */
/* Bit 5-3 */
#define EM_PAGE_HI_CE0_INV		        0x00
#define EM_PAGE_HI_CE1_INV		        0x08
#define EM_PAGE_HI_CE2_INV		        0x10
#define EM_PAGE_HI_CE3_INV		        0x18
/* Bit 2-0 extended page address bits for EMA 25-23 */

#define EM_PAGE_INC_DEC  			   (0x03)
/* Bit 7-0 2's complemnt to add to page address */

/*-----------------------------------------------------------------------------*/
/* MCU-A15 Control Register 												   */
/*-----------------------------------------------------------------------------*/
#define MCU_A15CTRL_REG  			   (0x04)			/* default 0x00 */
/* Bit 7-0 */
#define MCU_A15_WD_MASK					0x80
#define MCU_A15_EXT_RST_MASK		    0x40
#define MCU_A15_LOWBAT_MASK			    0x20
#define MCU_A15_RESERVED				0x10
#define MCU_A15_DCDIS_NMI_MASK	        0x08
#define MCU_A15_SIRQ_MASK				0x04
#define MCU_A15_NMI_MASK				0x02
#define MCU_A15_A15_MASK				0x01

/*-----------------------------------------------------------------------------*/
/* Internal MROM SRAM Page Register																					   */
/*-----------------------------------------------------------------------------*/
#define INTERNAL_MROM_SRAM_PAGE_REG	   (0x05)			/* default 0x00 */
/* Bit 7-0 */
#define INT_MROM_SRAM_LOW_IPM_TO_MCU	0x80
#define INT_MROM_SRAM_HI_IPM_TO_MCU		0x40
#define INT_MROM_SRAM_LOW_IDM_TO_MCU	0x20
#define INT_MROM_SRAM_HI_IDM_TO_MCU		0x10
#define INT_MROM_SRAM_CONCURRENT_MODE	0x08
/* Bit 3-0 Extended IPM/IDM Page address bit */
#define INT_MROM_SRAM_ZRAM2				0x7
#define INT_MROM_SRAM_IDM_HIGH_BLOCK	0x6
#define INT_MROM_SRAM_IDM_MID_BLOCK		0x5
#define INT_MROM_SRAM_IDM_LOW_BLOCK		0x4
#define INT_MROM_SRAM_IDM_RESERVED		0x3
#define INT_MROM_SRAM_IPM_HIGH_BLOCK	0x2
#define INT_MROM_SRAM_IPM_MID_BLOCK		0x1
#define INT_MROM_SRAM_IPM_LOW_BLOCK		0x0

/*-----------------------------------------------------------------------------*/
/*DMA1 CNTRL																																	 */
/*-----------------------------------------------------------------------------*/
#define DMA1_SRCADDR0_REG    (0x06)
#define DMA1_SRCADDR1_REG    (0x07)
#define DMA1_SRCADDR2_REG    (0x08)
#define DMA1_SRCADDR3_REG    (0x09)
#define DMA1_SRCADDR4_REG    (0x0a)
#define DMA1_IPMSRC_REG      (0x0a)
#define DMA1_IDMSRC_REG      (0x0a)
#define DMA1_ZRAM2SRC_REG    (0x0a)

#define DMA1_DSTADDR0_REG    (0x0b)
#define DMA1_DSTADDR1_REG    (0x0c)
#define DMA1_DSTADDR2_REG    (0x0d)
#define DMA1_DSTADDR3_REG    (0x0e)
#define DMA1_DSTADDR4_REG    (0x0f)
#define DMA1_IPMDST_REG      (0x0f)
#define DMA1_IDMDST_REG      (0x0f)
#define DMA1_ZRAM2DST_REG    (0x0f)

#define DMA1_CNTR_LO_REG     (0x10)
#define DMA1_CNTR_HI_REG     (0x11)
#define DMA1_MODE_REG        (0x12)
#define DMA1_COMMAND_REG     (0x13)

/*-----------------------------------------------------------------------------*/
/*DMA2 CNTRL																																	 */
/*-----------------------------------------------------------------------------*/
#define DMA2_SRCADDR0_REG    (0x14)
#define DMA2_SRCADDR1_REG    (0x15)
#define DMA2_SRCADDR2_REG    (0x16)
#define DMA2_SRCADDR3_REG    (0x17)
#define DMA2_SRCADDR4_REG    (0x18)
#define DMA2_IPMSRC_REG      (0x18)
#define DMA2_IDMSRC_REG      (0x18)
#define DMA2_ZRAM2SRC_REG    (0x18)

#define DMA2_DSTADDR0_REG    (0x19)
#define DMA2_DSTADDR1_REG    (0x1a)
#define DMA2_DSTADDR2_REG    (0x1b)
#define DMA2_DSTADDR3_REG    (0x1c)
#define DMA2_DSTADDR4_REG    (0x1d)
#define DMA2_IPMDST_REG      (0x1d)
#define DMA2_IDMDST_REG      (0x1d)
#define DMA2_ZRAM2DST_REG    (0x1d)

#define DMA2_CNTR_LO_REG     (0x1e)
#define DMA2_CNTR_HI_REG     (0x1f)
#define DMA2_MODE_REG        (0x20)
#define DMA2_COMMAND_REG     (0x21)

/*-----------------------------------------------------------------------------*/
/*CTC1		  																																	 */
/*-----------------------------------------------------------------------------*/
#define CTC1_PRESCALE_REG                   (0x22)			/* default 0xxxxxxxb */
/* Bit 7 Enable/Disable */
#define CTC1_ENABLE				       0x80
/* Bit 6-0 Prescaler.  Clk source of CTC1 is from undivided MCU CLK */
/* Divide by 1 - 128 */

#define CTC1_PERIOD_LO_REG                  (0x23)			/* default 0xXX */
/* Bit 7-0 TPERIOD[7:0] period low register */

#define CTC1_PERIOD_HI_REG                  (0x24)			/* default 0xXX */
/* Bit 7-0 TPERIOD[15:8] period high register */

/*-----------------------------------------------------------------------------*/
/*IRQ STATUS																																	 */
/*-----------------------------------------------------------------------------*/
#define IRQ_STATUS_REG       		        0x25   		/* default 0x00 */
/*write 1 to any bit will clear the bit */
#define IRQ_STATUS_CTC_PENDING				0x80
#define IRQ_STATUS_DMA2_HALF_PENDING		0x40
#define IRQ_STATUS_DMA2_END_PENDING			0x20
#define IRQ_STATUS_DMA1_HALF_PENDING		0x10
#define IRQ_STATUS_DMA1_END_PENDING			0x08
#define IRQ_STATUS_SIRQ_PENDING				0x04
#define IRQ_STATUS_RESERVED					0x02
#define IRQ_STATUS_RESET_DMA1_DMA2			0x01	/* Reset the DMA statemachine.  Reverts to 0 */

/*-----------------------------------------------------------------------------*/
/*MASTER INTERRUPT CONTROL																										 */
/*-----------------------------------------------------------------------------*/
#define MINT_STATUS_REG    		       (0x26)		/* default 0x00 */
/* Bit 7-0 */
#define MINT_STATUS_ADC					0x80
#define MINT_STATUS_KEYBOARD		    0x40
#define MINT_STATUS_RTC					0x20
#define MINT_STATUS_DMA_CTC			    0x10
#define MINT_STATUS_I2C					0x08
#define MINT_STATUS_SIRQ				0x08
#define MINT_STATUS_SPI					0x08
#define MINT_STATUS_USB					0x04
#define MINT_STATUS_UART				0x02
#define MINT_STATUS_IR					0x02
#define MINT_STATUS_SPDIF				0x02
#define MINT_STATUS_DSP					0x01

#define MINT_ENABLE_REG      		   (0x27)		/* default 0x00 */
/* Bit 7-0 */
#define MINT_ENABLE_ADC					0x80
#define MINT_ENABLE_KEYBOARD		    0x40
#define MINT_ENABLE_RTC					0x20
#define MINT_ENABLE_DMA_CTC			    0x10
#define MINT_ENABLE_I2C					0x08
#define MINT_ENABLE_SIRQ				0x08
#define MINT_ENABLE_SPI					0x08
#define MINT_ENABLE_USB					0x04
#define MINT_ENABLE_UART				0x02
#define MINT_ENABLE_IR					0x02
#define MINT_ENABLE_SPDIF				0x02
#define MINT_ENABLE_DSP					0x01

/*-----------------------------------------------------------------------------*/
/*DSP CONTROL																																	 */
/*-----------------------------------------------------------------------------*/
#define DSP_STATUS_CONTROL_REG	0x2e
#define DSP_BOOTMODE_REG    		0x2f
#define DSP_HIP_REG0        		0x30
#define DSP_HIP_REG1        		0x31
#define DSP_HIP_REG2        		0x32
#define DSP_HIP_REG3        		0x33
#define DSP_HIP_REG4        		0x34
#define DSP_HIP_REG5        		0x35
#define DSP_HIP_REG6        		0x36
#define DSP_HIP_REG7        		0x37

/*-----------------------------------------------------------------------------*/
/*USB INTERFACE																																 */
/*-----------------------------------------------------------------------------*/
#define USB_RESCTRL_REG     	   (0x3e)
/* Bit 7 */
#define USB_RESCTRL_ENABLE          0x80
/* Bit 6-3 Reserved*/
/* Bit 2-0 */
#define USB_RESCTRL_1_8_K           0x07
#define USB_RESCTRL_1_7_K           0x06
#define USB_RESCTRL_1_6_K           0x05
#define USB_RESCTRL_1_5_K           0x04
#define USB_RESCTRL_1_4_K           0x03
#define USB_RESCTRL_1_3_K           0x02
#define USB_RESCTRL_1_2_K           0x01
#define USB_RESCTRL_1_1_K           0x00