pll_top.v

来自「静态pll实验程序」· Verilog 代码 · 共 31 行

// PLL_top.v

module PLL_top(clk_48M,KEY_PWN,LOCK,GLA,POWERDN);
input       clk_48M;

input       KEY_PWN;

output      LOCK;
output      GLA;

output      POWERDN;

wire       POWERDOWN;
assign     POWERDN = POWERDOWN;


//--------例化ctrl_PLL--------------
ctrl_PLL u1(
             .clk(clk_48M),
             .KEY_PWN(KEY_PWN),
             .POWERDOWN(POWERDOWN)

             );
//------例化PLL_075M----------------
PLL_0P75M    u2(
             .POWERDOWN(POWERDOWN),
             .CLKA(clk_48M),
             .LOCK(LOCK),
             .GLA(GLA));

endmodule