stdout.log

来自「静态pll实验程序」· LOG 代码 · 共 37 行

License checkout: synplify_pc

Starting:    D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\bin\mbin\synplify.exe
Install:     D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1
Date:        Mon Nov 24 22:05:56 2008
Version:     9.4A1


Arguments:   -product synplify PLL_top_syn.prj
ProductType: synplify

License checkout: synplify_pc
License: synplify_pc node-locked 



Running synthesis on PLL_top_syn:synthesis

log file: "D:\Actelprj\Static_PLL\synthesis\PLL_top.srr"


Running Verilog Compiler...

Verilog Compiler Completed
Return Code: 0


Running Fusion Mapper...

Fusion Mapper Completed
Return Code: 0


exit status=0