pll_top.tlg

来自「静态pll实验程序」· TLG 代码 · 共 17 行

Selecting top level module PLL_top
@N: CG364 :"D:\Actelprj\Static_PLL\hdl\ctrl_PLL.v":8:7:8:14|Synthesizing module ctrl_PLL

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":260:7:260:12|Synthesizing module PLLINT

@N: CG364 :"D:\Actelprj\Static_PLL\smartgen\PLL_0P75M\PLL_0P75M.v":5:7:5:15|Synthesizing module PLL_0P75M

@N: CG364 :"D:\Actelprj\Static_PLL\hdl\PLL_top.v":3:7:3:13|Synthesizing module PLL_top

@W: CS148 :"D:\Actelprj\Static_PLL\hdl\PLL_top.v":25:13:25:14|Undriven input OADIVRST, tying to 0