📄 designer.log
字号:
Actel Designer Software
Version: 8.4.0.33
Release: v8.4
Netlist Reading Time = 1.0 seconds
Imported the files:
D:\Actelprj\LCD_1602\synthesis\LCD_Top.edn
D:\Actelprj\LCD_1602\synthesis\LCD_Top_sdc.sdc
The Import command succeeded ( 00:00:06 )
Info: The design D:\Actelprj\LCD_1602\designer\impl1\LCD_Top.adb was last modified by software
version 8.4.0.33.
Opened an existing Libero design D:\Actelprj\LCD_1602\designer\impl1\LCD_Top.adb.
'BA_NAME' set to 'LCD_Top_ba'
The Execute Script command succeeded ( 00:00:00 )
=====================================================================
Parameters used to run compile:
===============================
Family : Fusion
Device : AFS600
Package : 256 FBGA
Source : D:\Actelprj\LCD_1602\synthesis\LCD_Top.edn
D:\Actelprj\LCD_1602\synthesis\LCD_Top_sdc.sdc
Format : EDIF
Topcell : LCD_Top
Speed grade : STD
Temp : 0:25:70
Voltage : 1.58:1.50:1.42
Keep Existing Physical Constraints : Yes
Keep Existing Timing Constraints : Yes
pdc_abort_on_error : Yes
pdc_eco_display_unmatched_objects : No
pdc_eco_max_warnings : 10000
demote_globals : No
promote_globals : No
localclock_max_shared_instances : 12
localclock_buffer_tree_max_fanout : 12
combine_register : Yes
delete_buffer_tree : No
report_high_fanout_nets_limit : 10
=====================================================================
Compile starts ...
Warning: CMP201: Net U1/U1/Core_GLB drives no load.
Warning: CMP201: Net U1/U1/Core_GLC drives no load.
Warning: CMP201: Net U1/U1/Core_LOCK drives no load.
Warning: CMP201: Net U1/U1/Core_YB drives no load.
Warning: CMP201: Net U1/U1/Core_YC drives no load.
Netlist Optimization Report
===========================
Optimized macros:
- Dangling net drivers: 0
- Buffers: 2
- Inverters: 1
- Tieoff: 0
- Logic combining: 23
Total macros optimized 26
Warning: CMP503: Remapped 22 enable flip-flop(s) to a 2-tile implementation because the CLR/PRE
pin on the enable flip-flop is not being driven by a global net.
There were 0 error(s) and 6 warning(s) in this design.
=====================================================================
Reading previous post-compile physical placement constraints.
There were 0 error(s) and 0 warning(s).
=====================================================================
Compile report:
===============
CORE Used: 560 Total: 13824 (4.05%)
IO (W/ clocks) Used: 22 Total: 119 (18.49%)
Differential IO Used: 0 Total: 58 (0.00%)
GLOBAL (Chip+Quadrant) Used: 6 Total: 18 (33.33%)
PLL Used: 1 Total: 2 (50.00%)
RAM/FIFO Used: 0 Total: 24 (0.00%)
Low Static ICC Used: 0 Total: 1 (0.00%)
FlashROM Used: 0 Total: 1 (0.00%)
User JTAG Used: 0 Total: 1 (0.00%)
RC oscillator Used: 0 Total: 1 (0.00%)
XTL oscillator Used: 0 Total: 1 (0.00%)
NVM Used: 0 Total: 2 (0.00%)
AB Used: 0 Total: 1 (0.00%)
AnalogIO Used: 0 Total: 46 (0.00%)
VRPSM Used: 0 Total: 1 (0.00%)
No-Glitch MUX Used: 0 Total: 2 (0.00%)
Global Information:
Type | Used | Total
----------------|--------|-------------
Chip global | 6 | 6 (100.00%)
Quadrant global | 0 | 12 (0.00%)
Core Information:
Type | Instances | Core tiles
--------|--------------|-----------
COMB | 330 | 330
SEQ | 230 | 230
I/O Function:
Type | w/o register | w/ register | w/ DDR register
------------------------------|---------------|--------------|----------------
Input I/O | 3 | 0 | 0
Output I/O | 19 | 0 | 0
Bidirectional I/O | 0 | 0 | 0
Differential Input I/O Pairs | 0 | 0 | 0
Differential Output I/O Pairs | 0 | 0 | 0
I/O Technology:
| Voltages | I/Os
--------------------------------|-------|-------|-------|--------|--------------
I/O Standard(s) | Vcci | Vref | Input | Output | Bidirectional
--------------------------------|-------|-------|-------|--------|--------------
LVTTL | 3.30v | N/A | 3 | 19 | 0
I/O Placement:
Locked : 13 ( 59.09% )
Placed : 0
UnPlaced: 9 ( 40.91% )
Warning: Only some I/Os are locked
Net information report:
=======================
The following nets have been assigned to a chip global resource:
Fanout Type Name
--------------------------
188 CLK_NET Net : clk_LCD
Driver: U1/clk_BUF_RNI4SU/U_CLKSRC
Source: NETLIST
87 INT_NET Net : U2/state_RNIOSR4_0[4]
Driver: U2/state_RNIOSR4_0[4]/U_CLKSRC
Source: NETLIST
86 INT_NET Net : U2/state[4]
Driver: U2/state_RNIQ4A[4]/U_CLKSRC
Source: NETLIST
78 INT_NET Net : U2/state[5]
Driver: U2/state_RNIR4A[5]/U_CLKSRC
Source: NETLIST
77 INT_NET Net : U2/state_RNIQSR4_0[6]
Driver: U2/state_RNIQSR4_0[6]/U_CLKSRC
Source: NETLIST
11 CLK_NET Net : U1/clk_counter
Driver: U1/U1/Core
Source: ESSENTIAL
High fanout nets in the post compile netlist:
Fanout Type Name
--------------------------
34 CLK_NET Net : clk_48M_c
Driver: clk_48M_pad
19 SET/RESET_NET Net : rst_c
Driver: rst_pad
18 SET/RESET_NET Net : rst_c_0
Driver: rst_pad_RNI106
18 INT_NET Net : U3/clk_ena
Driver: U3/cnt_RNI58011[21]
17 SET/RESET_NET Net : reset_c
Driver: reset_pad
17 SET/RESET_NET Net : reset_c_0
Driver: reset_pad_RNI5OA
12 INT_NET Net : U2/state[6]
Driver: U2/state[6]
11 INT_NET Net : U2/disp_count_RNI2J14[2]
Driver: U2/disp_count_RNI2J14[2]
9 INT_NET Net : U2/state_ns[7]
Driver: U2/state_RNIRSL4[7]
9 INT_NET Net : U2/N_156
Driver: U2/state_RNIPSL4_0[6]
Nets that are candidates for clock assignment and the resulting fanout:
Fanout Type Name
--------------------------
36 SET/RESET_NET Net : rst_c
Driver: rst_pad
34 CLK_NET Net : clk_48M_c
Driver: clk_48M_pad
33 SET/RESET_NET Net : reset_c
Driver: reset_pad
18 INT_NET Net : U3/clk_ena
Driver: U3/cnt_RNI58011[21]
13 INT_NET Net : U2/disp_count_RNI2J14[2]
Driver: U2/disp_count_RNI2J14[2]
12 INT_NET Net : U2/state[6]
Driver: U2/state[6]
9 INT_NET Net : U2/state_ns[7]
Driver: U2/state_RNIRSL4[7]
9 INT_NET Net : U2/N_156
Driver: U2/state_RNIPSL4_0[6]
8 INT_NET Net : U3/U1.DWACT_FINC_E[0]
Driver: U3/un6_cnt_I_16
8 INT_NET Net : U1/clk_BUF6
Driver: U1/count_RNIGNLH[1]
SDC Import: Begin processing constraints...
SDC Import: End processing constraints
The Compile command succeeded ( 00:00:05 )
Info: I/O Bank Assigner detected (1) out of (5) I/O Bank(s) with locked I/O technologies.
Running I/O Bank Assigner.
I/O Bank Assigner completed successfully.
Planning global net placement...
Global net placement completed successfully.
o - o - o - o - o - o
Timing-driven Placer Started: Thu Jan 29 17:17:39 2009
Placer Finished: Thu Jan 29 17:17:49 2009
Total Placer CPU Time: 00:00:10
o - o - o - o - o - o
Timing-driven Router
Design: LCD_Top Started: Thu Jan 29 17:17:58 2009
Iterative improvement...
Timing-driven Router completed successfully.
Design: LCD_Top
Finished: Thu Jan 29 17:19:07 2009
Total CPU Time: 00:01:08 Total Elapsed Time: 00:01:09
o - o - o - o - o - o
Loading the Timing data for the design.
Finished loading the Timing data.
TIMER: Max delay timing requirements have been met.
The Layout command succeeded ( 00:01:39 )
Warning: The following files already exist:
D:\Actelprj\LCD_1602\designer\impl1\LCD_Top.pdb
Do you want to replace the files? [YES]
The Export-map command succeeded ( 00:00:34 )
Warning: Overwriting the existing file: D:\Actelprj\LCD_1602\designer\impl1\LCD_Top.pdb.
Wrote to the file: D:\Actelprj\LCD_1602\designer\impl1\LCD_Top.pdb
CHECKSUM: 4EBE
The Generate programming file command succeeded ( 00:00:39 )
Warning: Files
D:\Actelprj\LCD_1602\designer\impl1\LCD_Top_ba.sdf
D:\Actelprj\LCD_1602\designer\impl1\LCD_Top_ba.v
already exist.
Do you want to replace the files? [YES]
Warning: Overwriting the existing file: ./LCD_Top_ba.sdf.
Back-annotated to the file(s):
.\LCD_Top_ba.sdf
The Back-Annotate command succeeded ( 00:00:01 )
Design saved to file D:\Actelprj\LCD_1602\designer\impl1\LCD_Top.adb.
Design closed.
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -