lcd_top_ba.sdf

液晶屏lcd1602的使用历程

     (PORT B (2.52:3.12:3.41) (2.43:3.02:3.29))
     (IOPATH B Y (4.17:5.24:5.91) (4.59:5.76:6.50))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U3\/cnt\[4\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.60:3.22:3.52) (2.53:3.14:3.43))
     (PORT CLK (33.04:40.97:44.73) (31.72:39.33:42.94))
     (IOPATH CLK Q (3.71:4.67:5.27) (4.61:5.79:6.54))
     (PORT CLR (24.75:30.69:33.50) (23.86:29.58:32.30))
     (IOPATH CLR Q () (3.76:4.73:5.34))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (5.03:6.31:7.13))
     (SETUP (negedge D) (posedge CLK) (5.03:6.31:7.13))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.67:4.31:4.31))
     (WIDTH (negedge CLK) (4.06:4.77:4.77))
     (WIDTH (posedge CLR) (2.52:2.96:2.96))
     (RECOVERY (negedge CLR) (posedge CLK) (2.10:2.63:2.97))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "MX2")
 (INSTANCE U2\/DB8\[2\]\/U0)
 (DELAY
  (ABSOLUTE
     (PORT A (2.52:3.12:3.41) (2.43:3.02:3.29))
     (IOPATH A Y (4.01:5.04:5.68) (4.08:5.13:5.79))
     (PORT B (2.52:3.12:3.41) (2.43:3.02:3.29))
     (IOPATH B Y (4.13:5.19:5.86) (4.03:5.07:5.72))
     (PORT S (17.07:21.16:23.11) (16.26:20.16:22.01))
     (IOPATH S Y (3.38:4.50:5.08) (3.30:4.60:5.20))
  )
 )
 )
 (CELL
 (CELLTYPE "IOIN_IB")
 (INSTANCE clk_48M_pad\/U0\/U1)
 (DELAY
  (ABSOLUTE
     (PORT YIN (0.00:0.00:0.00) (0.00:0.00:0.00))
     (IOPATH YIN Y (0.31:0.38:0.43) (0.28:0.35:0.40))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_RNO\[9\])
 (DELAY
  (ABSOLUTE
     (PORT A (5.72:7.09:7.74) (5.87:7.28:7.95))
     (IOPATH A Y (2.56:3.22:3.63) (3.58:4.50:5.08))
     (PORT B (2.70:3.35:3.66) (2.59:3.22:3.51))
     (IOPATH B Y (4.17:5.24:5.91) (4.59:5.76:6.50))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[82\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.50:3.09:3.38) (2.41:2.99:3.26))
     (PORT CLK (5.84:7.24:7.91) (5.98:7.41:8.09))
     (IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
     (PORT E (5.65:7.01:7.65) (5.78:7.16:7.82))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
     (SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (4.06:4.77:4.77))
     (WIDTH (negedge CLK) (3.67:4.31:4.31))
     (SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
     (SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "AND3")
 (INSTANCE U3\/un6_cnt_I_155)
 (DELAY
  (ABSOLUTE
     (PORT A (11.55:14.32:15.64) (11.01:13.65:14.91))
     (IOPATH A Y (3.70:4.65:5.25) (3.27:4.11:4.64))
     (PORT B (7.71:9.56:10.44) (7.33:9.09:9.92))
     (IOPATH B Y (4.40:5.53:6.24) (4.28:5.37:6.07))
     (PORT C (2.56:3.18:3.47) (2.46:3.05:3.33))
     (IOPATH C Y (4.70:5.90:6.66) (4.52:5.68:6.41))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U2\/DB8\[2\]\/U1)
 (DELAY
  (ABSOLUTE
     (PORT D (2.52:3.12:3.41) (2.43:3.02:3.29))
     (PORT CLK (5.87:7.28:7.95) (5.99:7.43:8.11))
     (IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
     (PORT CLR (25.06:31.06:33.92) (23.79:29.50:32.21))
     (IOPATH CLR Q () (3.76:4.73:5.34))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.80:4.77:5.39))
     (SETUP (negedge D) (posedge CLK) (4.05:5.08:5.74))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (4.06:4.77:4.77))
     (WIDTH (negedge CLK) (3.67:4.31:4.31))
     (WIDTH (posedge CLR) (2.52:2.96:2.96))
     (RECOVERY (negedge CLR) (posedge CLK) (2.10:2.63:2.97))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[106\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.50:3.09:3.38) (2.39:2.96:3.23))
     (PORT CLK (5.85:7.26:7.92) (5.97:7.40:8.08))
     (IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
     (PORT E (5.67:7.03:7.67) (5.80:7.19:7.85))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
     (SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (4.06:4.77:4.77))
     (WIDTH (negedge CLK) (3.67:4.31:4.31))
     (SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
     (SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_RNO\[34\])
 (DELAY
  (ABSOLUTE
     (PORT A (5.76:7.15:7.80) (5.86:7.27:7.93))
     (IOPATH A Y (2.56:3.22:3.63) (3.58:4.50:5.08))
     (PORT B (2.50:3.09:3.38) (2.41:2.99:3.26))
     (IOPATH B Y (4.17:5.24:5.91) (4.59:5.76:6.50))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[84\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.50:3.09:3.38) (2.39:2.96:3.23))
     (PORT CLK (5.84:7.24:7.91) (5.98:7.41:8.09))
     (IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
     (PORT E (5.67:7.02:7.67) (5.78:7.17:7.83))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
     (SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (4.06:4.77:4.77))
     (WIDTH (negedge CLK) (3.67:4.31:4.31))
     (SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
     (SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[53\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.50:3.09:3.38) (2.39:2.96:3.23))
     (PORT CLK (6.06:7.51:8.20) (6.15:7.62:8.32))
     (IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
     (PORT E (5.70:7.07:7.72) (5.82:7.22:7.88))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
     (SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (4.06:4.77:4.77))
     (WIDTH (negedge CLK) (3.67:4.31:4.31))
     (SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
     (SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_RNO\[49\])
 (DELAY
  (ABSOLUTE
     (PORT A (2.50:3.09:3.38) (2.41:2.99:3.26))
     (IOPATH A Y (4.17:5.24:5.91) (4.45:5.59:6.31))
     (PORT B (5.67:7.03:7.68) (5.79:7.18:7.83))
     (IOPATH B Y (2.87:3.60:4.07) (2.72:3.42:3.86))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[75\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.50:3.09:3.38) (2.39:2.96:3.23))
     (PORT CLK (5.80:7.19:7.85) (5.93:7.35:8.03))
     (IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
     (PORT E (5.69:7.05:7.70) (5.81:7.20:7.86))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
     (SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (4.06:4.77:4.77))
     (WIDTH (negedge CLK) (3.67:4.31:4.31))
     (SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
     (SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[33\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.62:3.25:3.55) (2.55:3.17:3.46))
     (PORT CLK (5.87:7.28:7.95) (5.99:7.43:8.11))
     (IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
     (PORT E (5.73:7.10:7.75) (5.85:7.25:7.92))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
     (SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (4.06:4.77:4.77))
     (WIDTH (negedge CLK) (3.67:4.31:4.31))
     (SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
     (SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U3\/cnt\[15\])
 (DELAY
  (ABSOLUTE
     (PORT D (7.69:9.54:10.41) (6.88:8.53:9.32))
     (PORT CLK (33.62:41.68:45.51) (32.33:40.08:43.76))
     (IOPATH CLK Q (3.71:4.67:5.27) (4.61:5.79:6.54))
     (PORT CLR (9.72:12.05:13.16) (8.66:10.74:11.73))
     (IOPATH CLR Q () (3.76:4.73:5.34))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (5.03:6.31:7.13))
     (SETUP (negedge D) (posedge CLK) (5.03:6.31:7.13))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.67:4.31:4.31))
     (WIDTH (negedge CLK) (4.06:4.77:4.77))
     (WIDTH (posedge CLR) (2.52:2.96:2.96))
     (RECOVERY (negedge CLR) (posedge CLK) (2.10:2.63:2.97))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "MX2")
 (INSTANCE U2\/disp_count\[3\]\/U0)
 (DELAY
  (ABSOLUTE
     (PORT A (2.50:3.09:3.38) (2.41:2.99:3.26))
     (IOPATH A Y (4.70:5.90:6.66) (4.36:5.48:6.19))
     (PORT B (3.53:4.38:4.79) (3.27:4.05:4.42))
     (IOPATH B Y (4.13:5.19:5.86) (4.03:5.07:5.72))
     (PORT S (22.74:28.19:30.78) (21.17:26.25:28.66))
     (IOPATH S Y (2.57:4.25:4.80) (2.62:3.51:3.96))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_RNO\[108\])
 (DELAY
  (ABSOLUTE
     (PORT A (10.63:13.18:14.39) (10.18:12.63:13.79))
     (IOPATH A Y (4.17:5.24:5.91) (4.45:5.59:6.31))
     (PORT B (5.59:6.93:7.57) (5.71:7.08:7.73))
     (IOPATH B Y (2.87:3.60:4.07) (2.72:3.42:3.86))
  )
 )
 )
 (CELL
 (CELLTYPE "MX2")
 (INSTANCE U2\/RS\/U0)
 (DELAY
  (ABSOLUTE
     (PORT A (16.71:20.71:22.62) (15.85:19.65:21.45))
     (IOPATH A Y (4.70:5.90:6.66) (4.36:5.48:6.19))
     (PORT B (2.50:3.09:3.38) (2.39:2.96:3.23))
     (IOPATH B Y (4.13:5.19:5.86) (4.03:5.07:5.72))
     (PORT S (2.40:2.98:3.25) (2.30:2.85:3.11))
     (IOPATH S Y (2.57:4.25:4.80) (2.62:3.51:3.96))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_RNO\[64\])
 (DELAY
  (ABSOLUTE
     (PORT A (7.00:8.67:9.47) (6.25:7.75:8.46))
     (IOPATH A Y (4.17:5.24:5.91) (4.45:5.59:6.31))
     (PORT B (5.59:6.93:7.57) (5.71:7.08:7.73))
     (IOPATH B Y (2.87:3.60:4.07) (2.72:3.42:3.86))
  )
 )
 )
 (CELL
 (CELLTYPE "XA1")
 (INSTANCE U3\/cnt_RNO\[22\])
 (DELAY
  (ABSOLUTE
     (PORT A (2.40:2.98:3.25) (2.30:2.85:3.11))
     (IOPATH A Y (2.44:4.27:4.82) (2.80:3.60:4.07))
     (PORT B (3.02:3.74:4.09) (2.86:3.54:3.87))
     (IOPATH B Y (4.52:5.93:6.69) (5.16:8.75:9.87))
     (PORT C (13.04:16.17:17.65) (12.05:14.94:16.31))
     (IOPATH C Y (4.55:5.71:6.45) (5.03:6.31:7.13))
  )
 )
 )
 (CELL
 (CELLTYPE "IOPAD_TRI")
 (INSTANCE LED_pad\[1\]\/U0\/U0)
 (DELAY
  (ABSOLUTE
     (PORT D (0.00:0.00:0.00) (0.00:0.00:0.00))
     (IOPATH D PAD (18.19:23.71:28.69) (23.94:30.87:36.67))
     (PORT E (0.00:0.00:0.00) (0.00:0.00:0.00))
     (IOPATH E PAD (18.19:27.57:32.75) (23.59:30.87:37.35))
  )
  (PATHPULSE D PAD (2.00:2.00:2.00) (2.00:2.00:2.00))
  (PATHPULSE E PAD (2.00:2.00:2.00) (2.00:2.00:2.00))
 )
 (TIMINGCHECK 
     (WIDTH (posedge D) (20.00:20.00:20.00))
     (WIDTH (negedge D) (20.00:20.00:20.00))
     (WIDTH (posedge E) (20.00:20.00:20.00))
     (WIDTH (negedge E) (20.00:20.00:20.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[41\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.52:3.12:3.41) (2.41:2.99:3.26))
     (PORT CLK (5.78:7.17:7.83) (5.92:7.34:8.01))
     (IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
     (PORT E (5.73:7.10:7.75) (5.87:7.27:7.94))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
     (SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (4.06:4.77:4.77))
     (WIDTH (negedge CLK) (3.67:4.31:4.31))
     (SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
     (SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYP