📄 lcd_top_ba.sdf
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(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "LCD_Top")
(DATE "Thu Jan 29 17:20:19 2009")
(VENDOR "ACTEL")
(PROGRAM "Actel Designer Software, Release v8.4 Copyright (C) 1989-2008 Actel Corp. ")
(VERSION "8.4.0.33")
(DIVIDER /)
(VOLTAGE 1.58:1.50:1.43)
(PROCESS "best:nom:worst")
(TEMPERATURE 0:25:70)
(TIMESCALE 100ps)
//Data source: Silicon verified
(CELL
(CELLTYPE "NOR2A")
(INSTANCE U2\/Data_First_Buf_RNO\[51\])
(DELAY
(ABSOLUTE
(PORT A (2.50:3.09:3.38) (2.41:2.99:3.26))
(IOPATH A Y (4.17:5.24:5.91) (4.45:5.59:6.31))
(PORT B (5.68:7.04:7.69) (5.80:7.18:7.84))
(IOPATH B Y (2.87:3.60:4.07) (2.72:3.42:3.86))
)
)
)
(CELL
(CELLTYPE "NOR2A")
(INSTANCE U2\/Data_Second_Buf_RNISH51\[3\])
(DELAY
(ABSOLUTE
(PORT A (3.02:3.74:4.09) (2.86:3.54:3.87))
(IOPATH A Y (4.17:5.24:5.91) (4.45:5.59:6.31))
(PORT B (5.62:6.97:7.61) (5.76:7.14:7.79))
(IOPATH B Y (2.87:3.60:4.07) (2.72:3.42:3.86))
)
)
)
(CELL
(CELLTYPE "NOR2A")
(INSTANCE U2\/Data_First_Buf_RNO\[35\])
(DELAY
(ABSOLUTE
(PORT A (2.50:3.09:3.38) (2.41:2.99:3.26))
(IOPATH A Y (4.17:5.24:5.91) (4.45:5.59:6.31))
(PORT B (5.59:6.93:7.57) (5.71:7.08:7.73))
(IOPATH B Y (2.87:3.60:4.07) (2.72:3.42:3.86))
)
)
)
(CELL
(CELLTYPE "NOR2A")
(INSTANCE U2\/Data_Second_Buf_RNO\[100\])
(DELAY
(ABSOLUTE
(PORT A (2.50:3.09:3.38) (2.41:2.99:3.26))
(IOPATH A Y (4.17:5.24:5.91) (4.45:5.59:6.31))
(PORT B (5.66:7.02:7.66) (5.77:7.16:7.82))
(IOPATH B Y (2.87:3.60:4.07) (2.72:3.42:3.86))
)
)
)
(CELL
(CELLTYPE "OR2")
(INSTANCE U2\/Data_Second_Buf_RNO\[35\])
(DELAY
(ABSOLUTE
(PORT A (5.59:6.93:7.56) (5.71:7.08:7.73))
(IOPATH A Y (2.56:3.22:3.63) (3.58:4.50:5.08))
(PORT B (2.50:3.09:3.38) (2.41:2.99:3.26))
(IOPATH B Y (4.17:5.24:5.91) (4.59:5.76:6.50))
)
)
)
(CELL
(CELLTYPE "DFN1E0")
(INSTANCE U2\/Data_Second_Buf\[93\])
(DELAY
(ABSOLUTE
(PORT D (2.50:3.09:3.38) (2.39:2.96:3.23))
(PORT CLK (5.82:7.21:7.87) (5.94:7.37:8.04))
(IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
(PORT E (5.70:7.07:7.72) (5.83:7.22:7.89))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
(SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
(HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
(WIDTH (posedge CLK) (4.06:4.77:4.77))
(WIDTH (negedge CLK) (3.67:4.31:4.31))
(SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
(SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
(HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
)
)
(CELL
(CELLTYPE "NOR3C")
(INSTANCE U3\/cnt_RNIPQQ6\[4\])
(DELAY
(ABSOLUTE
(PORT A (2.89:3.58:3.91) (2.73:3.38:3.69))
(IOPATH A Y (3.70:4.65:5.25) (3.27:4.11:4.64))
(PORT B (8.78:10.89:11.89) (8.32:10.32:11.26))
(IOPATH B Y (4.40:5.53:6.24) (4.28:5.37:6.07))
(PORT C (5.40:6.69:7.31) (5.03:6.23:6.80))
(IOPATH C Y (5.30:6.65:7.51) (4.81:6.04:6.81))
)
)
)
(CELL
(CELLTYPE "DFN1C1")
(INSTANCE U3\/cnt\[24\])
(DELAY
(ABSOLUTE
(PORT D (2.50:3.09:3.38) (2.41:2.99:3.26))
(PORT CLK (33.62:41.68:45.51) (32.33:40.08:43.76))
(IOPATH CLK Q (3.71:4.67:5.27) (4.61:5.79:6.54))
(PORT CLR (33.09:41.03:44.79) (31.13:38.59:42.14))
(IOPATH CLR Q () (3.76:4.73:5.34))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (5.03:6.31:7.13))
(SETUP (negedge D) (posedge CLK) (5.03:6.31:7.13))
(HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
(WIDTH (posedge CLK) (3.67:4.31:4.31))
(WIDTH (negedge CLK) (4.06:4.77:4.77))
(WIDTH (posedge CLR) (2.52:2.96:2.96))
(RECOVERY (negedge CLR) (posedge CLK) (2.10:2.63:2.97))
(HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
)
)
(CELL
(CELLTYPE "DFN1E0")
(INSTANCE U2\/Data_First_Buf\[62\])
(DELAY
(ABSOLUTE
(PORT D (2.50:3.09:3.38) (2.39:2.96:3.23))
(PORT CLK (5.75:7.13:7.79) (5.90:7.32:7.99))
(IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
(PORT E (5.67:7.02:7.67) (5.78:7.17:7.83))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
(SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
(HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
(WIDTH (posedge CLK) (4.06:4.77:4.77))
(WIDTH (negedge CLK) (3.67:4.31:4.31))
(SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
(SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
(HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE U3\/un6_cnt_I_94)
(DELAY
(ABSOLUTE
(PORT A (2.89:3.58:3.91) (2.73:3.38:3.69))
(IOPATH A Y (3.45:4.33:4.88) (3.63:4.56:5.15))
(PORT B (3.02:3.74:4.09) (2.86:3.54:3.87))
(IOPATH B Y (3.64:4.57:5.16) (4.43:5.56:6.28))
)
)
)
(CELL
(CELLTYPE "DFN1C1")
(INSTANCE U2\/DB8\[7\]\/U1)
(DELAY
(ABSOLUTE
(PORT D (2.50:3.09:3.38) (2.39:2.96:3.23))
(PORT CLK (5.73:7.10:7.75) (5.87:7.28:7.95))
(IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
(PORT CLR (27.10:33.60:36.69) (26.13:32.40:35.38))
(IOPATH CLR Q () (3.76:4.73:5.34))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (3.80:4.77:5.39))
(SETUP (negedge D) (posedge CLK) (4.05:5.08:5.74))
(HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
(WIDTH (posedge CLK) (4.06:4.77:4.77))
(WIDTH (negedge CLK) (3.67:4.31:4.31))
(WIDTH (posedge CLR) (2.52:2.96:2.96))
(RECOVERY (negedge CLR) (posedge CLK) (2.10:2.63:2.97))
(HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
)
)
(CELL
(CELLTYPE "NOR2A")
(INSTANCE U2\/Data_First_Buf_RNO\[26\])
(DELAY
(ABSOLUTE
(PORT A (2.56:3.18:3.47) (2.46:3.05:3.33))
(IOPATH A Y (4.17:5.24:5.91) (4.45:5.59:6.31))
(PORT B (5.70:7.07:7.72) (5.84:7.24:7.90))
(IOPATH B Y (2.87:3.60:4.07) (2.72:3.42:3.86))
)
)
)
(CELL
(CELLTYPE "DFN1E0")
(INSTANCE U2\/Data_Second_Buf\[56\])
(DELAY
(ABSOLUTE
(PORT D (2.60:3.22:3.52) (2.51:3.11:3.39))
(PORT CLK (5.77:7.16:7.82) (5.91:7.33:8.00))
(IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
(PORT E (5.64:6.99:7.63) (5.76:7.14:7.80))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
(SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
(HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
(WIDTH (posedge CLK) (4.06:4.77:4.77))
(WIDTH (negedge CLK) (3.67:4.31:4.31))
(SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
(SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
(HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
)
)
(CELL
(CELLTYPE "DFN1E0")
(INSTANCE U2\/Data_First_Buf\[64\])
(DELAY
(ABSOLUTE
(PORT D (2.70:3.35:3.66) (2.62:3.24:3.54))
(PORT CLK (6.24:7.73:8.44) (6.34:7.86:8.58))
(IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
(PORT E (5.93:7.35:8.03) (6.06:7.51:8.20))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
(SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
(HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
(WIDTH (posedge CLK) (4.06:4.77:4.77))
(WIDTH (negedge CLK) (3.67:4.31:4.31))
(SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
(SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
(HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
)
)
(CELL
(CELLTYPE "DFN1E0")
(INSTANCE U2\/Data_First_Buf\[37\])
(DELAY
(ABSOLUTE
(PORT D (2.50:3.09:3.38) (2.41:2.99:3.26))
(PORT CLK (5.72:7.09:7.74) (5.87:7.27:7.94))
(IOPATH CLK Q (4.09:5.14:5.81) (5.20:6.53:7.37))
(PORT E (5.67:7.04:7.68) (5.81:7.20:7.86))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (4.05:5.08:5.74))
(SETUP (negedge D) (posedge CLK) (3.80:4.77:5.39))
(HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
(WIDTH (posedge CLK) (4.06:4.77:4.77))
(WIDTH (negedge CLK) (3.67:4.31:4.31))
(SETUP (posedge E) (posedge CLK) (3.07:3.85:4.35))
(SETUP (negedge E) (posedge CLK) (4.29:5.39:6.08))
(HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
(HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
)
)
(CELL
(CELLTYPE "IOPAD_TRI")
(INSTANCE DB8_pad\[4\]\/U0\/U0)
(DELAY
(ABSOLUTE
(PORT D (0.00:0.00:0.00) (0.00:0.00:0.00))
(IOPATH D PAD (18.19:23.71:28.69) (23.94:30.87:36.67))
(PORT E (0.00:0.00:0.00) (0.00:0.00:0.00))
(IOPATH E PAD (18.19:27.57:32.75) (23.59:30.87:37.35))
)
(PATHPULSE D PAD (2.00:2.00:2.00) (2.00:2.00:2.00))
(PATHPULSE E PAD (2.00:2.00:2.00) (2.00:2.00:2.00))
)
(TIMINGCHECK
(WIDTH (posedge D) (20.00:20.00:20.00))
(WIDTH (negedge D) (20.00:20.00:20.00))
(WIDTH (posedge E) (20.00:20.00:20.00))
(WIDTH (negedge E) (20.00:20.00:20.00))
)
)
(CELL
(CELLTYPE "IOTRI_OB_EB")
(INSTANCE RS_pad\/U0\/U1)
(DELAY
(ABSOLUTE
(PORT D (13.38:16.59:18.11) (12.99:16.10:17.58))
(IOPATH D DOUT (4.60:5.78:6.52) (4.65:5.84:6.59))
)
)
)
(CELL
(CELLTYPE "OR2")
(INSTANCE U2\/Data_Second_Buf_RNO\[65\])
(DELAY
(ABSOLUTE
(PORT A (5.76:7.15:7.80) (5.86:7.27:7.93))
(IOPATH A Y (2.56:3.22:3.63) (3.58:4.50:5.08))
(PORT B (2.50:3.09:3.38) (2.41:2.99:3.26))
(IOPATH B Y (4.17:5.24:5.91) (4.59:5.76:6.50))
)
)
)
(CELL
(CELLTYPE "IOPAD_IN")
(INSTANCE clk_48M_pad\/U0\/U0)
(DELAY
(ABSOLUTE
(PORT PAD (0.00:0.00:0.00) (0.00:0.00:0.00))
(IOPATH PAD Y (6.44:8.39:10.16) (4.50:5.80:6.89))
)
(PATHPULSE PAD Y (2.00:2.00:2.00) (2.00:2.00:2.00))
)
(TIMINGCHECK
(WIDTH (posedge PAD) (20.00:20.00:20.00))
(WIDTH (negedge PAD) (20.00:20.00:20.00))
)
)
(CELL
(CELLTYPE "BUFF")
(INSTANCE rst_pad_RNI106)
(DELAY
(ABSOLUTE
(PORT A (21.33:26.45:28.88) (20.46:25.36:27.69))
(IOPATH A Y (3.29:4.13:4.66) (3.79:4.76:5.37))
)
)
)
(CELL
(CELLTYPE "NOR2A")
(INSTANCE U2\/Data_Second_Buf_RNO\[92\])
(DELAY
(ABSOLUTE
(PORT A (2.50:3.09:3.38) (2.41:2.99:3.26))
(IOPATH A Y (4.17:5.24:5.91) (4.45:5.59:6.31))
(PORT B (5.66:7.02:7.66) (5.77:7.16:7.82))
(IOPATH B Y (2.87:3.60:4.07) (2.72:3.42:3.86))
)
)
)
(CELL
(CELLTYPE "NOR2B")
(INSTANCE U2\/LCD_EN_Sel_RNI1JT2)
(DELAY
(ABSOLUTE
(PORT A (5.78:7.17:7.82) (5.88:7.29:7.96))
(IOPATH A Y (3.45:4.33:4.88) (3.63:4.56:5.15))
(PORT B (5.78:7.17:7.83) (5.40:6.70:7.32))
(IOPATH B Y (4.17:5.24:5.91) (4.45:5.59:6.31))
)
)
)
(CELL
(CELLTYPE "OR2")
(INSTANCE U2\/Data_Second_Buf_RNO\[28\])
(DELAY
(ABSOLUTE
(PORT A (5.79:7.18:7.84) (5.88:7.29:7.95))
(IOPATH A Y (2.56:3.22:3.63) (3.58:4.50:5.08))
(PORT B (2.50:3.09:3.38) (2.41:2.99:3.26))
(IOPATH B Y (4.17:5.24:5.91) (4.59:5.76:6.50))
)
)
)
(CELL
(CELLTYPE "CLKSRC")
(INSTANCE U2\/state_RNIOSR4_0\[4\]\/U_CLKSRC)
(DELAY
(ABSOLUTE
(PORT A (8.76:10.86:11.86) (8.15:10.10:11.03))
(IOPATH A Y (7.58:9.52:10.74) (7.61:9.56:10.79))
)
)
)
(CELL
(CELLTYPE "MX2")
(INSTANCE U2\/disp_count\[0\]\/U0)
(DELAY
(ABSOLUTE
(PORT A (2.50:3.09:3.38) (2.41:2.99:3.26))
(IOPATH A Y (4.70:5.90:6.66) (4.36:5.48:6.19))
(PORT B (8.47:10.51:11.47) (7.67:9.51:10.38))
(IOPATH B Y (4.13:5.19:5.86) (4.03:5.07:5.72))
(PORT S (14.71:18.23:19.91) (13.82:17.14:18.71))
(IOPATH S Y (2.57:4.25:4.80) (2.62:3.51:3.96))
)
)
)
(CELL
(CELLTYPE "IOTRI_OB_EB")
(INSTANCE LED_pad\[1\]\/U0\/U1)
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