led.v

来自「液晶屏lcd1602的使用历程」· Verilog 代码 · 共 43 行

// LED.v
module LED(
           reset,           //异步复位
           clk_48M,         //48MHz时钟输入
           LED              //流水灯输出
           );     
parameter   cnt_top=24000000;

input             reset;                             
input             clk_48M;
output      [7:0] LED;

wire              clk_ena;     //时钟使能
reg         [7:0] LED;
reg         [24:0] cnt;

always @(posedge clk_48M or posedge reset)
begin
     if(reset)
        cnt     <=25'b0;
      else
         if(clk_ena)
             cnt   <=25'b0;
         else
             cnt    <=cnt+1'b1;
end
assign clk_ena=(cnt==cnt_top-1);     //获得0.5s的时钟使能

always @(posedge clk_48M or posedge reset)
begin
    if(reset)
       LED  <=8'hfe;
    else
        if(clk_ena)
        begin
           LED[7:1]  <=LED[6:0];    //每0.5s移动一位
           LED[0]     <=LED[7];
        end
end
           
endmodule