📄 lcd_top.srr
字号:
U1.un6_count_1.I_16 AND3 Y Out 0.516 2.232 -
U1\.DWACT_FINC_E[0] Net - - 1.211 - 6
U1.un6_count_1.I_48 AND3 A In - 3.443 -
U1.un6_count_1.I_48 AND3 Y Out 0.395 3.838 -
U1\.DWACT_FINC_E[4] Net - - 0.274 - 1
U1.un6_count_1.I_51 NOR2B B In - 4.111 -
U1.un6_count_1.I_51 NOR2B Y Out 0.534 4.645 -
N_4 Net - - 0.274 - 1
U1.un6_count_1.I_52 XOR2 A In - 4.919 -
U1.un6_count_1.I_52 XOR2 Y Out 0.415 5.334 -
I_52 Net - - 0.274 - 1
U1.count_RNO[9] NOR2B A In - 5.608 -
U1.count_RNO[9] NOR2B Y Out 0.415 6.023 -
count_3[9] Net - - 0.274 - 1
U1.count[9] DFN1C1 D In - 6.297 -
====================================================================================
Total path delay (propagation time + setup) of 6.755 is 3.361(49.8%) logic and 3.394(50.2%) route.
====================================
Detailed Report for Clock: Clock_Gen|clk_BUF_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------
U2.disp_count[1] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 Q disp_count[1] 0.627 0.665
U2.disp_count[0] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 Q disp_count_c0 0.627 0.863
U2.disp_count[2] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 Q disp_count[2] 0.627 1.082
U2.disp_count[3] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 Q disp_count[3] 0.627 1.440
U2.state[5] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state_0[5] 0.627 2.811
U2.state[6] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state[6] 0.627 3.571
U2.state[4] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state_0[4] 0.627 4.161
U2.state[1] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state[1] 0.627 5.840
U2.state[2] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state[2] 0.627 6.043
U2.state[7] Clock_Gen|clk_BUF_inferred_clock DFN1P1 Q state_i_0[7] 0.627 6.071
==================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------
U2.DB8[2] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 D N_160 9.542 0.665
U2.DB8[0] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 D DB8_6[0] 9.571 0.931
U2.DB8[1] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 D N_158 9.571 1.073
U2.Data_First_Buf[0] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E N_22 9.482 1.263
U2.Data_First_Buf[6] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E N_22 9.482 1.263
U2.Data_First_Buf[8] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E N_22 9.482 1.263
U2.Data_First_Buf[9] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E N_22 9.482 1.263
U2.Data_First_Buf[10] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E N_22 9.482 1.263
U2.Data_First_Buf[11] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E N_22 9.482 1.263
U2.Data_First_Buf[14] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E N_22 9.482 1.263
===================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.458
= Required time: 9.542
- Propagation time: 8.876
= Slack (critical) : 0.665
Number of logic level(s): 6
Starting point: U2.disp_count[1] / Q
Ending point: U2.DB8[2] / D
The start point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
The end point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
U2.disp_count[1] DFN1E0C1 Q Out 0.627 0.627 -
disp_count[1] Net - - 1.007 - 4
U2.disp_count_RNIIT02[3] NOR2B B In - 1.634 -
U2.disp_count_RNIIT02[3] NOR2B Y Out 0.534 2.168 -
state_ns_o2_i_a3_0[6] Net - - 0.274 - 1
U2.disp_count_RNI2J14[2] OR2B B In - 2.442 -
U2.disp_count_RNI2J14[2] OR2B Y Out 0.534 2.976 -
disp_count_RNI2J14[2] Net - - 1.512 - 11
U2.state_RNITNB4[5] OR2B B In - 4.487 -
U2.state_RNITNB4[5] OR2B Y Out 0.439 4.926 -
N_194 Net - - 0.328 - 2
U2.state_RNIPSL4_0[6] OR2A A In - 5.255 -
U2.state_RNIPSL4_0[6] OR2A Y Out 0.396 5.651 -
N_195 Net - - 1.420 - 9
U2.state_RNII105[3] OR2 B In - 7.071 -
U2.state_RNII105[3] OR2 Y Out 0.438 7.508 -
N_324 Net - - 0.328 - 2
U2.DB8_RNO[2] OA1B A In - 7.837 -
U2.DB8_RNO[2] OA1B Y Out 0.766 8.603 -
N_160 Net - - 0.274 - 1
U2.DB8[2] DFN1E0C1 D In - 8.876 -
===========================================================================================
Total path delay (propagation time + setup) of 9.335 is 4.192(44.9%) logic and 5.142(55.1%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell LCD_Top.verilog
Core Cell usage:
cell count area count*area
AND2 2 1.0 2.0
AND3 8 1.0 8.0
AO1C 1 1.0 1.0
AOI1 1 1.0 1.0
AX1E 1 1.0 1.0
BUFF 1 1.0 1.0
CLKINT 5 0.0 0.0
GND 4 0.0 0.0
INV 3 1.0 3.0
MX2 4 1.0 4.0
MX2B 3 1.0 3.0
MX2C 4 1.0 4.0
NOR2 3 1.0 3.0
NOR2A 68 1.0 68.0
NOR2B 11 1.0 11.0
NOR3A 1 1.0 1.0
NOR3C 3 1.0 3.0
OA1A 2 1.0 2.0
OA1B 1 1.0 1.0
OAI1 1 1.0 1.0
OR2 106 1.0 106.0
OR2A 4 1.0 4.0
OR2B 4 1.0 4.0
PLL 1 0.0 0.0
PLLINT 1 0.0 0.0
VCC 4 0.0 0.0
XA1 1 1.0 1.0
XNOR2 1 1.0 1.0
XOR2 9 1.0 9.0
DFN1C1 16 1.0 16.0
DFN1E0 174 1.0 174.0
DFN1E0C1 14 1.0 14.0
DFN1P1 3 1.0 3.0
----- ----------
TOTAL 465 450.0
IO Cell usage:
cell count
INBUF 2
OUTBUF 11
-----
TOTAL 13
Core Cells : 450 of 13824 (3%)
IO Cells : 13 of 172 (8%)
RAM/ROM Usage Summary
Block Rams : 0 of 24 (0%)
Mapper successful!
Process took 0h:00m:05s realtime, 0h:00m:03s cputime
# Thu Jan 29 16:31:10 2009
###########################################################]
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