📄 lcd_top.srr
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Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 88MB peak: 89MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 88MB peak: 89MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 88MB peak: 89MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 88MB peak: 89MB)
Finished preparing to map (Time elapsed 0h:00m:03s; Memory used current: 89MB peak: 89MB)
High Fanout Net Report
**********************
Driver Instance / Pin Name Fanout, notes
---------------------------------------------------------------------------
U2.state[5] / Q 83
U2.state[4] / Q 88
U2.un1_Data_Second_Buf_2_sqmuxa_i[0] / Y 84
U2.un1_Data_First_Buf_1_sqmuxa_i / Y 90
rst_pad / Y 36 : 33 asynchronous set/reset
===========================================================================
Promoting Net clk_LCD on CLKINT U1.clk_BUF_inferred_clock
Promoting Net U2.N_22 on CLKINT I_3
Promoting Net U2.state[4] on CLKINT I_4
Promoting Net U2.N_566 on CLKINT I_5
Promoting Net U2.state[5] on CLKINT I_6
Buffering rst_c, fanout 36 segments 2
Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 88MB peak: 89MB)
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 88MB peak: 89MB)
Added 1 Buffers
Added 0 Cells via replication
Added 0 Sequential Cells via replication
Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 88MB peak: 89MB)
Writing Analyst data base D:\Actelprj\LCD_1602\synthesis\LCD_Top.srm
@N: BN225 |Writing default property annotation file D:\Actelprj\LCD_1602\synthesis\LCD_Top.map.
Finished Writing Netlist Databases (Time elapsed 0h:00m:03s; Memory used current: 87MB peak: 89MB)
Writing EDIF Netlist and constraint files
Version 9.4A1
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:03s; Memory used current: 87MB peak: 89MB)
Found clock Clock_Gen|U1.clk_counter_inferred_clock with period 10.00ns
Found clock Clock_Gen|clk_BUF_inferred_clock with period 10.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jan 29 16:31:09 2009
#
Top view: LCD_Top
Library name: fusion
Operating conditions: COMWC-1 ( T = 70.0, V = 1.42, P = 1.48, tree_type = balanced_tree )
Requested Frequency: 100.0 MHz
Wire load mode: top
Wire load model: fusion
Paths requested: 5
Constraint File(s):
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: 0.665
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------------------------------
Clock_Gen|U1.clk_counter_inferred_clock 100.0 MHz 148.0 MHz 10.000 6.755 3.245 inferred Inferred_clkgroup_1
Clock_Gen|clk_BUF_inferred_clock 100.0 MHz 107.1 MHz 10.000 9.335 0.665 inferred Inferred_clkgroup_0
==============================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Clock_Gen|clk_BUF_inferred_clock Clock_Gen|clk_BUF_inferred_clock | 10.000 0.665 | No paths - | No paths - | No paths -
Clock_Gen|U1.clk_counter_inferred_clock Clock_Gen|U1.clk_counter_inferred_clock | 10.000 3.245 | No paths - | No paths - | No paths -
========================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: Clock_Gen|U1.clk_counter_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------
U1.count[1] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[1] 0.627 3.245
U1.count[2] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[2] 0.627 3.296
U1.count[0] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[0] 0.627 3.366
U1.count[3] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[3] 0.494 3.511
U1.count[6] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[6] 0.627 3.639
U1.count[4] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[4] 0.627 3.648
U1.count[5] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[5] 0.627 3.700
U1.count[7] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[7] 0.494 4.155
U1.count[9] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[9] 0.494 4.429
U1.count[8] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 Q count[8] 0.627 4.797
=============================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------
U1.count[9] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_3[9] 9.542 3.245
U1.count[0] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_3[0] 9.512 3.511
U1.count[3] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_3[3] 9.512 3.511
U1.count[5] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_3[5] 9.512 3.511
U1.count[6] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_3[6] 9.512 3.511
U1.count[7] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_3[7] 9.512 3.511
U1.count[8] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D count_3[8] 9.512 3.511
U1.clk_BUF Clock_Gen|U1.clk_counter_inferred_clock DFN1E0C1 E clk_BUF6 9.482 4.289
U1.count[4] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D I_20 9.542 4.602
U1.count[2] Clock_Gen|U1.clk_counter_inferred_clock DFN1C1 D I_9 9.542 6.330
==================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.458
= Required time: 9.542
- Propagation time: 6.297
= Slack (non-critical) : 3.245
Number of logic level(s): 5
Starting point: U1.count[1] / Q
Ending point: U1.count[9] / D
The start point is clocked by Clock_Gen|U1.clk_counter_inferred_clock [rising] on pin CLK
The end point is clocked by Clock_Gen|U1.clk_counter_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------
U1.count[1] DFN1C1 Q Out 0.627 0.627 -
count[1] Net - - 1.089 - 5
U1.un6_count_1.I_16 AND3 B In - 1.716 -
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