traplog.tlg

液晶屏lcd1602的使用历程

@N: CD630 :".\gentmp0a05828":4:7:4:9|Synthesizing work.top.gen 
@N: CD630 :"syng0a05828":1366:7:1366:9|Synthesizing work.inc.finc 
@W: CD638 :"syng0a05828":1387:9:1387:13|Signal carry is undriven 
@W: CD638 :"syng0a05828":1388:9:1388:12|Signal asup is undriven 
@W: CD638 :"syng0a05828":1388:15:1388:18|Signal ssup is undriven 
@N: CD630 :"syng0a05828":357:7:357:22|Synthesizing work.dwact_bl_fincdec.impl1 
@W: CD280 :"syng0a05828":369:12:369:14|Unbound component INV mapped to black box
@W: CD639 :"syng0a05828":474:9:474:9|Bit <19> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <20> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <21> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <22> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <23> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <24> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <25> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <26> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <27> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <30> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <31> of signal e is undriven 
@W: CD639 :"syng0a05828":474:9:474:9|Bit <32> of signal e is undriven 
@N: CD630 :"syng0a05828":191:7:191:20|Synthesizing work.dwact_tl_l2xor.impl1 
@W: CD280 :"syng0a05828":207:12:207:15|Unbound component AND3 mapped to black box
@W: CD280 :"syng0a05828":230:12:230:15|Unbound component XOR2 mapped to black box
@N: CD630 :"syng0a05828":230:12:230:15|Synthesizing work.xor2.syn_black_box 
Post processing for work.xor2.syn_black_box
@N: CD630 :"syng0a05828":207:12:207:15|Synthesizing work.and3.syn_black_box 
Post processing for work.and3.syn_black_box
Post processing for work.dwact_tl_l2xor.impl1
@N: CD630 :"syng0a05828":120:7:120:19|Synthesizing work.dwact_tl_and2.impl1 
@W: CD280 :"syng0a05828":137:10:137:13|Unbound component AND2 mapped to black box
@N: CD630 :"syng0a05828":137:10:137:13|Synthesizing work.and2.syn_black_box 
Post processing for work.and2.syn_black_box
Post processing for work.dwact_tl_and2.impl1
@N: CD630 :"syng0a05828":267:7:267:19|Synthesizing work.dwact_tl_and3.impl1 
Post processing for work.dwact_tl_and3.impl1
@N: CD630 :"syng0a05828":305:7:305:19|Synthesizing work.dwact_bl_xor2.impl1 
Post processing for work.dwact_bl_xor2.impl1
@N: CD630 :"syng0a05828":369:12:369:14|Synthesizing work.inv.syn_black_box 
Post processing for work.inv.syn_black_box
@N: CD630 :"syng0a05828":55:7:55:18|Synthesizing work.dwact_tl_vcc.impl1 
@W: CD280 :"syng0a05828":68:13:68:15|Unbound component VCC mapped to black box
@N: CD630 :"syng0a05828":68:13:68:15|Synthesizing work.vcc.syn_black_box 
Post processing for work.vcc.syn_black_box
Post processing for work.dwact_tl_vcc.impl1
Post processing for work.dwact_bl_fincdec.impl1
Post processing for work.inc.finc
Post processing for work.top.gen