lcd_top.srr

液晶屏lcd1602的使用历程

               PLL     1      0.0        0.0
            PLLINT     1      0.0        0.0
               VCC     5      0.0        0.0
               XA1     1      1.0        1.0
             XNOR2     1      1.0        1.0
              XOR2    33      1.0       33.0


            DFN1C1    41      1.0       41.0
            DFN1E0   164      1.0      164.0
          DFN1E0C1    15      1.0       15.0
          DFN1E0P1     7      1.0        7.0
            DFN1P1     3      1.0        3.0
                   -----          ----------
             TOTAL   580               563.0


  IO Cell usage:
              cell count
             INBUF     3
            OUTBUF    19
                   -----
             TOTAL    22


Core Cells         : 563 of 13824 (4%)
IO Cells           : 22 of 172 (13%)

  RAM/ROM Usage Summary
Block Rams : 0 of 24 (0%)

Mapper successful!
Process took 0h:00m:05s realtime, 0h:00m:03s cputime
# Thu Jan 29 17:10:53 2009

###########################################################]
$ Start of Compile
#Thu Jan 29 17:10:54 2009

Synplicity Verilog Compiler, version 1.0, Build 061R, built Jun 30 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@I::"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v"
@I::"D:\Actelprj\LCD_1602\smartgen\PLL_1M\PLL_1M.v"
@I::"D:\Actelprj\LCD_1602\hdl\Clock_Gen.v"
@I::"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v"
@I::"D:\Actelprj\LCD_1602\hdl\LED.v"
@I::"D:\Actelprj\LCD_1602\hdl\LCD_Top.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module LCD_Top
@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL

@N: CG364 :"D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\lib\proasic\fusion.v":260:7:260:12|Synthesizing module PLLINT

@N: CG364 :"D:\Actelprj\LCD_1602\smartgen\PLL_1M\PLL_1M.v":5:7:5:12|Synthesizing module PLL_1M

@N: CG364 :"D:\Actelprj\LCD_1602\hdl\Clock_Gen.v":4:7:4:15|Synthesizing module Clock_Gen

@N: CG179 :"D:\Actelprj\LCD_1602\hdl\Clock_Gen.v":34:27:34:33|Removing redundant assignment
@W: CS148 :"D:\Actelprj\LCD_1602\hdl\Clock_Gen.v":14:12:14:13|Undriven input OADIVRST, tying to 0
@N: CG364 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":6:7:6:16|Synthesizing module LCD_Driver

@A:"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Feedback mux created for signal Data_Second_Buf[111:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@A:"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Feedback mux created for signal Data_First_Buf[111:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[0] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[4] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[6] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[7] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[1] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[2] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[6] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[7] is always 0, optimizing ...
@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <7> of Data_First_Buf[111:0] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <6> of Data_First_Buf[111:0] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <4> of Data_First_Buf[111:0] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <0> of Data_First_Buf[111:0] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <7> of Data_Second_Buf[111:0] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <6> of Data_Second_Buf[111:0] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <2> of Data_Second_Buf[111:0] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <1> of Data_Second_Buf[111:0] 

@N: CG364 :"D:\Actelprj\LCD_1602\hdl\LED.v":2:7:2:9|Synthesizing module LED

@N: CG364 :"D:\Actelprj\LCD_1602\hdl\LCD_Top.v":4:7:4:13|Synthesizing module LCD_Top

@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[8] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[12] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[15] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[10] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[14] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[15] is always 0, optimizing ...
@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <15> of Data_Second_Buf[111:8] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <14> of Data_Second_Buf[111:8] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <10> of Data_Second_Buf[111:8] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <15> of Data_First_Buf[111:8] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <12> of Data_First_Buf[111:8] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <8> of Data_First_Buf[111:8] 

@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[22] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[23] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[20] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[23] is always 0, optimizing ...
@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <23> of Data_First_Buf[111:16] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <20> of Data_First_Buf[111:16] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <23> of Data_Second_Buf[111:16] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <22> of Data_Second_Buf[111:16] 

@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[30] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_Second_Buf[31] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[28] is always 0, optimizing ...
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[31] is always 0, optimizing ...
@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <31> of Data_First_Buf[111:24] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <28> of Data_First_Buf[111:24] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <31> of Data_Second_Buf[111:24] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <30> of Data_Second_Buf[111:24] 

@N: CL201 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 8 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
@W: CL189 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Register bit Data_First_Buf[39] is always 0, optimizing ...
@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <39> of Data_First_Buf[111:32] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <39> of Data_Second_Buf[111:32] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <3> of Data_First_Buf[3:1] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <2> of Data_First_Buf[3:1] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <5> of Data_Second_Buf[5:3] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <4> of Data_Second_Buf[5:3] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <11> of Data_First_Buf[11:9] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <10> of Data_First_Buf[11:9] 

@W: CL171 :"D:\Actelprj\LCD_1602\hdl\LCD_Driver.v":42:0:42:5|Pruning Register bit <13> of Data_Second_Buf[13:11] 

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jan 29 17:10:54 2009

###########################################################]
Synplicity Proasic Technology Mapper, Version 9.4.0, Build 055R, Built Jul  2 2008 07:11:59
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved
Product Version Version 9.4A1
@N: MF249 |Running in 32-bit mode.

Automatic dissolve at startup in view:work.Clock_Gen(verilog) of U1(PLL_1M)
@W: BN132 :"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Removing sequential instance U2.Data_Second_Buf[0],  because it is equivalent to instance U2.Data_Second_Buf[3]
Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB)

@N: MF238 :"d:\actelprj\lcd_1602\hdl\clock_gen.v":35:25:35:37|Found 10 bit incrementor, 'un6_count_1[9:0]'
@N:"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Found counter in view:work.LCD_Driver(verilog) inst disp_count[3:0]
Encoding state machine work.LCD_Driver(verilog)-state[7:0]
original code -> new code
   0000 -> 00000001
   0001 -> 00000010
   0010 -> 00000100
   0011 -> 00001000
   0100 -> 00010000
   0101 -> 00100000
   0110 -> 01000000
   0111 -> 10000000
@W: MO150 :"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Register big Data_Second_Buf[38] is always 0, optimizing ...
@W: MO150 :"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Register big Data_First_Buf[47] is always 0, optimizing ...
@W: MO150 :"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Register big Data_Second_Buf[47] is always 0, optimizing ...
@W: MO150 :"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Register big Data_Second_Buf[46] is always 0, optimizing ...
@W: MO150 :"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Register big Data_First_Buf[55] is always 0, optimizing ...
@W: MO150 :"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Register big Data_Second_Buf[55] is always 0, optimizing ...
@W: MO150 :"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Register big Data_Second_Buf[54] is always 0, optimizing ...
@W: MO150 :"d:\actelprj\lcd_1602\hdl\lcd_driver.v":42:0:42:5|Register big Data_First_Buf[63] is always 0, optimizing ...