📄 lcd_top.srr
字号:
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------
U2.disp_count[1] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 Q disp_count[1] 0.627 0.720
U2.disp_count[0] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 Q disp_count_c0 0.627 0.918
U2.disp_count[2] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 Q disp_count[2] 0.627 1.137
U2.disp_count[3] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 Q disp_count[3] 0.627 1.495
U2.state[5] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state_0[5] 0.627 2.866
U2.state[6] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state[6] 0.627 3.626
U2.state[4] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state_0[4] 0.627 4.161
U2.state[1] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state[1] 0.627 5.840
U2.state[2] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state[2] 0.627 6.043
U2.state[7] Clock_Gen|clk_BUF_inferred_clock DFN1P1 Q state_i_0[7] 0.627 6.071
==================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------------------
U2.DB8[2] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 D N_123 9.542 0.720
U2.DB8[0] Clock_Gen|clk_BUF_inferred_clock DFN1E0C1 D DB8_6[0] 9.571 0.931
U2.Data_First_Buf[1] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E state_RNIOSR4_0[4] 9.482 1.263
U2.Data_First_Buf[5] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E state_RNIOSR4_0[4] 9.482 1.263
U2.Data_First_Buf[9] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E state_RNIOSR4_0[4] 9.482 1.263
U2.Data_First_Buf[13] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E state_RNIOSR4_0[4] 9.482 1.263
U2.Data_First_Buf[14] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E state_RNIOSR4_0[4] 9.482 1.263
U2.Data_First_Buf[16] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E state_RNIOSR4_0[4] 9.482 1.263
U2.Data_First_Buf[17] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E state_RNIOSR4_0[4] 9.482 1.263
U2.Data_First_Buf[18] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E state_RNIOSR4_0[4] 9.482 1.263
=============================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.458
= Required time: 9.542
- Propagation time: 8.822
= Slack (critical) : 0.720
Number of logic level(s): 6
Starting point: U2.disp_count[1] / Q
Ending point: U2.DB8[2] / D
The start point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
The end point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
U2.disp_count[1] DFN1E0C1 Q Out 0.627 0.627 -
disp_count[1] Net - - 1.007 - 4
U2.disp_count_RNIIT02[3] NOR2B B In - 1.634 -
U2.disp_count_RNIIT02[3] NOR2B Y Out 0.534 2.168 -
state_ns_o2_i_a3_0[6] Net - - 0.274 - 1
U2.disp_count_RNI2J14[2] OR2B B In - 2.442 -
U2.disp_count_RNI2J14[2] OR2B Y Out 0.534 2.976 -
disp_count_RNI2J14[2] Net - - 1.512 - 11
U2.state_RNITNB4[5] OR2B B In - 4.487 -
U2.state_RNITNB4[5] OR2B Y Out 0.439 4.926 -
N_155 Net - - 0.328 - 2
U2.state_RNIPSL4_0[6] OR2A A In - 5.255 -
U2.state_RNIPSL4_0[6] OR2A Y Out 0.396 5.651 -
N_156 Net - - 1.420 - 9
U2.DB8_RNO_0[2] OR2 B In - 7.071 -
U2.DB8_RNO_0[2] OR2 Y Out 0.438 7.508 -
N_585 Net - - 0.274 - 1
U2.DB8_RNO[2] OA1B A In - 7.782 -
U2.DB8_RNO[2] OA1B Y Out 0.766 8.548 -
N_123 Net - - 0.274 - 1
U2.DB8[2] DFN1E0C1 D In - 8.822 -
===========================================================================================
Total path delay (propagation time + setup) of 9.280 is 4.192(45.2%) logic and 5.088(54.8%) route.
====================================
Detailed Report for Clock: LCD_Top|clk_48M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
U3.cnt[1] LCD_Top|clk_48M DFN1C1 Q cnt[1] 0.627 1.913
U3.cnt[0] LCD_Top|clk_48M DFN1C1 Q cnt[0] 0.627 1.947
U3.cnt[2] LCD_Top|clk_48M DFN1C1 Q cnt[2] 0.627 2.007
U3.cnt[3] LCD_Top|clk_48M DFN1C1 Q cnt[3] 0.627 2.097
U3.cnt[4] LCD_Top|clk_48M DFN1C1 Q cnt[4] 0.627 2.098
U3.cnt[15] LCD_Top|clk_48M DFN1C1 Q cnt[15] 0.627 2.120
U3.cnt[5] LCD_Top|clk_48M DFN1C1 Q cnt[5] 0.627 2.150
U3.cnt[9] LCD_Top|clk_48M DFN1C1 Q cnt[9] 0.627 2.239
U3.cnt[10] LCD_Top|clk_48M DFN1C1 Q cnt[10] 0.627 2.406
U3.cnt[7] LCD_Top|clk_48M DFN1C1 Q cnt[7] 0.627 2.415
===================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------
U3.cnt[12] LCD_Top|clk_48M DFN1C1 D cnt_3[12] 9.542 1.913
U3.cnt[9] LCD_Top|clk_48M DFN1C1 D cnt_3[9] 9.512 2.052
U3.cnt[10] LCD_Top|clk_48M DFN1C1 D cnt_3[10] 9.512 2.052
U3.cnt[13] LCD_Top|clk_48M DFN1C1 D cnt_3[13] 9.512 2.052
U3.cnt[17] LCD_Top|clk_48M DFN1C1 D cnt_3[17] 9.512 2.052
U3.cnt[18] LCD_Top|clk_48M DFN1C1 D cnt_3[18] 9.512 2.052
U3.cnt[19] LCD_Top|clk_48M DFN1C1 D cnt_3[19] 9.512 2.052
U3.cnt[21] LCD_Top|clk_48M DFN1C1 D cnt_3[21] 9.512 2.052
U3.cnt[22] LCD_Top|clk_48M DFN1C1 D cnt_3[22] 9.512 2.052
U3.cnt[24] LCD_Top|clk_48M DFN1C1 D cnt_3[24] 9.512 2.052
======================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.458
= Required time: 9.542
- Propagation time: 7.628
= Slack (non-critical) : 1.913
Number of logic level(s): 5
Starting point: U3.cnt[1] / Q
Ending point: U3.cnt[12] / D
The start point is clocked by LCD_Top|clk_48M [rising] on pin CLK
The end point is clocked by LCD_Top|clk_48M [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------
U3.cnt[1] DFN1C1 Q Out 0.627 0.627 -
cnt[1] Net - - 1.211 - 6
U3.un6_cnt.I_16 AND3 B In - 1.838 -
U3.un6_cnt.I_16 AND3 Y Out 0.516 2.354 -
U1\.DWACT_FINC_E[0] Net - - 1.395 - 8
U3.un6_cnt.I_62 AND3 A In - 3.749 -
U3.un6_cnt.I_62 AND3 Y Out 0.395 4.144 -
U1\.DWACT_FINC_E[6] Net - - 1.299 - 7
U3.un6_cnt.I_72 NOR2B B In - 5.442 -
U3.un6_cnt.I_72 NOR2B Y Out 0.534 5.976 -
N_70 Net - - 0.274 - 1
U3.un6_cnt.I_73 XOR2 A In - 6.250 -
U3.un6_cnt.I_73 XOR2 Y Out 0.415 6.665 -
I_73 Net - - 0.274 - 1
U3.cnt_RNO[12] NOR2B A In - 6.939 -
U3.cnt_RNO[12] NOR2B Y Out 0.415 7.355 -
cnt_3[12] Net - - 0.274 - 1
U3.cnt[12] DFN1C1 D In - 7.628 -
===================================================================================
Total path delay (propagation time + setup) of 8.087 is 3.361(41.6%) logic and 4.725(58.4%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell LCD_Top.verilog
Core Cell usage:
cell count area count*area
AND2 10 1.0 10.0
AND3 42 1.0 42.0
AO1C 1 1.0 1.0
AX1E 1 1.0 1.0
BUFF 3 1.0 3.0
CLKINT 5 0.0 0.0
GND 5 0.0 0.0
INV 4 1.0 4.0
MX2 5 1.0 5.0
MX2B 3 1.0 3.0
MX2C 3 1.0 3.0
NOR2 5 1.0 5.0
NOR2A 102 1.0 102.0
NOR2B 29 1.0 29.0
NOR3A 3 1.0 3.0
NOR3C 10 1.0 10.0
OA1A 1 1.0 1.0
OA1B 1 1.0 1.0
OAI1 1 1.0 1.0
OR2 65 1.0 65.0
OR2A 4 1.0 4.0
OR2B 5 1.0 5.0
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