lcd_1602.prj

液晶屏lcd1602的使用历程

KEY LIBERO "8.4"
KEY CAPTURE "8.4.0.33"
KEY DEFAULT_IMPORT_LOC "D:\Actelprj\LED\stimulus"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "Fusion"
KEY VendorTechnology_Die "IR6X6M2"
KEY VendorTechnology_Package "fg256"
KEY ProjectLocation "D:\Actelprj\LCD_1602"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "LCD_Top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\designer\impl1\LCD_Top.adb,adb"
STATE="ood"
TIME="1233220823"
SIZE="359424"
ENDFILE
VALUE "<project>\designer\impl1\LCD_Top.pdb,pdb"
STATE="ood"
TIME="1233220809"
SIZE="115200"
ENDFILE
VALUE "<project>\designer\impl1\LCD_Top_ba.sdf,ba_sdf"
STATE="ood"
TIME="1233220819"
SIZE="331082"
ENDFILE
VALUE "<project>\designer\impl1\LCD_Top_ba.v,ba_hdl"
STATE="ood"
TIME="1233220819"
SIZE="103907"
ENDFILE
VALUE "<project>\hdl\Clock_Gen.v,hdl"
STATE="utd"
TIME="1233217520"
SIZE="1132"
ENDFILE
VALUE "<project>\hdl\LCD_Driver.v,hdl"
STATE="utd"
TIME="1233562331"
SIZE="5779"
ENDFILE
VALUE "<project>\hdl\LCD_Top.v,hdl"
STATE="utd"
TIME="1233220232"
SIZE="674"
ENDFILE
VALUE "<project>\hdl\LED.v,hdl"
STATE="utd"
TIME="1233219791"
SIZE="941"
ENDFILE
VALUE "<project>\smartgen\PLL_1M\PLL_1M.cxf,actgen_cxf"
STATE="utd"
TIME="1233217461"
SIZE="1627"
ENDFILE
VALUE "<project>\smartgen\PLL_1M\PLL_1M.gen,gen"
STATE="utd"
TIME="1233217457"
SIZE="481"
PARENT="<project>\smartgen\PLL_1M\PLL_1M.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\PLL_1M\PLL_1M.log,log"
STATE="utd"
TIME="1233217461"
SIZE="3195"
PARENT="<project>\smartgen\PLL_1M\PLL_1M.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\PLL_1M\PLL_1M.v,hdl"
STATE="utd"
TIME="1233217461"
SIZE="1775"
PARENT="<project>\smartgen\PLL_1M\PLL_1M.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\synthesis\LCD_Top.edn,syn_edn"
STATE="ood"
TIME="1233220260"
SIZE="271660"
ENDFILE
VALUE "<project>\synthesis\LCD_Top_drc.rpt,log"
STATE="utd"
TIME="1233220309"
SIZE="7844"
ENDFILE
VALUE "<project>\synthesis\LCD_Top_sdc.sdc,syn_sdc"
STATE="ood"
TIME="1233220260"
SIZE="380"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "LCD_Top::work"
FILE "<project>\hdl\LCD_Top.v,hdl"
LIST ProjectState5.1
LIST Impl1
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\LCD_Top.edn,syn_edn"
VALUE "<project>\synthesis\LCD_Top_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\LCD_Top.v,syn_hdl"
VALUE "<project>\phy_synthesis\LCD_Top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\LCD_Top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\LCD_Top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\LCD_Top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\LCD_Top_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\LCD_Top.adb,adb"
VALUE "<project>\designer\impl1\LCD_Top.prb,prb"
VALUE "<project>\designer\impl1\LCD_Top.stp,stp"
VALUE "<project>\designer\impl1\LCD_Top_fp\LCD_Top.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=TRUE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole
Tool=CoreConsole v1.3 or later
Location=coreconsole
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\bin\Synplify.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=D:\Actel\Libero\Libero_v8.4\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=D:\Actel\Libero\Libero_v8.4\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=
Tool=
Location=
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=D:\Actel\Libero\Libero_v8.4\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "LCD_Top::work"
LIST Impl1
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\LCD_Top.edn,syn_edn"
VALUE "<project>\synthesis\LCD_Top_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\LCD_Top.v,syn_hdl"
VALUE "<project>\phy_synthesis\LCD_Top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\LCD_Top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\LCD_Top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\LCD_Top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\LCD_Top_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\LCD_Top.adb,adb"
VALUE "<project>\designer\impl1\LCD_Top.prb,prb"
VALUE "<project>\designer\impl1\LCD_Top.stp,stp"
VALUE "<project>\designer\impl1\LCD_Top_fp\LCD_Top.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
FILE:<project>\hdl\Clock_Gen.v,hdl
FILE:<project>\hdl\LCD_Driver.v,hdl
FILE:<project>\hdl\LCD_Top.v,hdl
FILE:<project>\hdl\LED.v,hdl
ACTIVE_VIEW:1
ENDLIST