ide_ext.mod

非常优秀的CPLD源代码

MODEL
MODEL_VERSION "v1998.8";
DESIGN "IDE_EXT";

/* port names and type */
INPUT S:PIN62 = NRD;
INPUT S:PIN61 = NCS4;
INPUT S:PIN63 = NWE;
INPUT S:PIN60 = NCS3;
INPUT S:PIN59 = NCS2;
INPUT S:PIN22 = ADDR2;
INPUT S:PIN24 = ADDR3;
INPUT S:PIN25 = ADDR4;
INPUT S:PIN27 = ADDR5;
INPUT S:PIN31 = ADDR6;
INPUT S:PIN64 = NRST;
INPUT S:PIN58 = IDE_INT;
INPUT S:PIN43 = IO_IDE_INT;
TRIOUT S:PIN44 = DATA<0>;
TRIOUT S:PIN45 = DATA<1>;
TRIOUT S:PIN46 = DATA<2>;
TRIOUT S:PIN47 = DATA<3>;
TRIOUT S:PIN48 = DATA<4>;
TRIOUT S:PIN49 = DATA<5>;
TRIOUT S:PIN50 = DATA<6>;
TRIOUT S:PIN51 = DATA<7>;
OUTPUT S:PIN33 = BUF_OE;
OUTPUT S:PIN32 = BUF_DIR;
OUTPUT S:PIN11 = IO_IDE_DA<0>;
OUTPUT S:PIN8 = IDE_DA<0>;
OUTPUT S:PIN12 = IO_IDE_DA<1>;
OUTPUT S:PIN9 = IDE_DA<1>;
OUTPUT S:PIN13 = IO_IDE_DA<2>;
OUTPUT S:PIN10 = IDE_DA<2>;
OUTPUT S:PIN6 = IDE_IOR;
OUTPUT S:PIN5 = IDE_IOW;
OUTPUT S:PIN15 = IO_IDE_CS0;
OUTPUT S:PIN1 = IDE_CS0;
OUTPUT S:PIN16 = IO_IDE_CS1;
OUTPUT S:PIN4 = IDE_CS1;
OUTPUT S:PIN19 = IO_IDE_IOR;
OUTPUT S:PIN18 = IO_IDE_IOW;
OUTPUT S:PIN20 = IO_IDE_RST;
OUTPUT S:PIN2 = IDE_RST;
OUTPUT S:PIN52 = IRQ0;
OUTPUT S:PIN56 = IRQ3;
OUTPUT S:PIN57 = NWAIT;

/* timing arc definitions */
NRD_BUF_DIR_delay: DELAY NRD BUF_DIR;
NCS4_BUF_OE_delay: DELAY NCS4 BUF_OE;
NCS3_BUF_OE_delay: DELAY NCS3 BUF_OE;
NCS2_BUF_OE_delay: DELAY NCS2 BUF_OE;
NCS4_DATA<0>_delay: DELAY (ENABLE_HIGH) NCS4 DATA<0>;
NRD_DATA<0>_delay: DELAY (ENABLE_HIGH) NRD DATA<0>;
NRD_DATA<1>_delay: DELAY (ENABLE_HIGH) NRD DATA<1>;
NCS4_DATA<1>_delay: DELAY (ENABLE_HIGH) NCS4 DATA<1>;
NCS4_DATA<2>_delay: DELAY (ENABLE_HIGH) NCS4 DATA<2>;
NRD_DATA<2>_delay: DELAY (ENABLE_HIGH) NRD DATA<2>;
NRD_DATA<3>_delay: DELAY (ENABLE_HIGH) NRD DATA<3>;
NCS4_DATA<3>_delay: DELAY (ENABLE_HIGH) NCS4 DATA<3>;
NCS4_DATA<4>_delay: DELAY (ENABLE_HIGH) NCS4 DATA<4>;
NRD_DATA<4>_delay: DELAY (ENABLE_HIGH) NRD DATA<4>;
NRD_DATA<5>_delay: DELAY (ENABLE_HIGH) NRD DATA<5>;
NCS4_DATA<5>_delay: DELAY (ENABLE_HIGH) NCS4 DATA<5>;
NRD_DATA<6>_delay: DELAY (ENABLE_HIGH) NRD DATA<6>;
NCS4_DATA<6>_delay: DELAY (ENABLE_HIGH) NCS4 DATA<6>;
NRD_DATA<7>_delay: DELAY (ENABLE_HIGH) NRD DATA<7>;
NCS4_DATA<7>_delay: DELAY (ENABLE_HIGH) NCS4 DATA<7>;
ADDR5_IDE_CS0_delay: DELAY ADDR5 IDE_CS0;
ADDR6_IDE_CS1_delay: DELAY ADDR6 IDE_CS1;
ADDR2_IDE_DA<0>_delay: DELAY ADDR2 IDE_DA<0>;
ADDR3_IDE_DA<1>_delay: DELAY ADDR3 IDE_DA<1>;
ADDR4_IDE_DA<2>_delay: DELAY ADDR4 IDE_DA<2>;
NCS2_IDE_IOR_delay: DELAY NCS2 IDE_IOR;
NRD_IDE_IOR_delay: DELAY NRD IDE_IOR;
NWE_IDE_IOW_delay: DELAY NWE IDE_IOW;
NCS2_IDE_IOW_delay: DELAY NCS2 IDE_IOW;
NRST_IDE_RST_delay: DELAY NRST IDE_RST;
ADDR5_IO_IDE_CS0_delay: DELAY ADDR5 IO_IDE_CS0;
ADDR6_IO_IDE_CS1_delay: DELAY ADDR6 IO_IDE_CS1;
ADDR2_IO_IDE_DA<0>_delay: DELAY ADDR2 IO_IDE_DA<0>;
ADDR3_IO_IDE_DA<1>_delay: DELAY ADDR3 IO_IDE_DA<1>;
ADDR4_IO_IDE_DA<2>_delay: DELAY ADDR4 IO_IDE_DA<2>;
NRD_IO_IDE_IOR_delay: DELAY NRD IO_IDE_IOR;
NCS3_IO_IDE_IOR_delay: DELAY NCS3 IO_IDE_IOR;
NWE_IO_IDE_IOW_delay: DELAY NWE IO_IDE_IOW;
NCS3_IO_IDE_IOW_delay: DELAY NCS3 IO_IDE_IOW;
NRST_IO_IDE_RST_delay: DELAY NRST IO_IDE_RST;
IDE_INT_IRQ0_delay: DELAY IDE_INT IRQ0;
IO_IDE_INT_IRQ3_delay: DELAY IO_IDE_INT IRQ3;

/* timing check arc definitions */

ENDMODEL