i2c_sl~2.lct

IIC控制器的verilog实现

[Device]
Family = lc4k;
PartNumber = LC4128V-75T144C;
Package = 144TQFP;
PartType = LC4128V;
Speed = -7.5;
Operating_condition = COM;
Status = Production;
EN_PinGLB = yes;
EN_PinMacrocell = yes;
Default_Device_IO_Types = LVCMOS33, -;

[Revision]
Parent = lc4k128v.lci;
DATE = 08/26/2005;
TIME = 13:14:25;
Source_Format = Schematic_Verilog_HDL;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]

[IO Types]
layer = OFF;

[Pullup]

[Slewrate]

[Region]

[Timing Constraints]
layer = OFF;

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[Pin attributes list]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[ORP Bypass]

[PLL Assignments]

[Register Powerup]

[global constraints list]

[Global Constraints Process Update]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[Constraint Version]
version = 1.0;

[Node attribute]
layer = OFF;

[SYMBOL/MODULE attribute]
layer = OFF;

[Nodal Constraints]
layer = OFF;