hw.c

via framebuffer driver

	case INTERFACE_DFP_LOW:
		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
			break;

		if (set_iga == IGA1) {
			viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
			viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
		} else {
			viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
			viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
		}

		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
		dvi_patch_skew_dvp_low();
		break;

	case INTERFACE_TMDS:
		if (set_iga == IGA1) {
			viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
		} else {
			viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
		}
		break;
	}

	if (set_iga == IGA2) {
		enable_second_display_channel();
		/* Disable LCD Scaling */
		viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
	}
}

static void set_lcd_output_path(int set_iga, int output_interface)
{
	DEBUG_MSG(KERN_INFO
		  "set_lcd_output_path, iga:%d,out_interface:%d\n",
		  set_iga, output_interface);
	switch (set_iga) {
	case IGA1:
		viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
		viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);

		disable_second_display_channel();
		break;

	case IGA2:
		viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
		viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);

		enable_second_display_channel();
		break;

	case IGA1_IGA2:
		viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
		viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);

		disable_second_display_channel();
		break;
	}

	switch (output_interface) {
	case INTERFACE_DVP0:
		if (set_iga == IGA1) {
			viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
		} else {
			viafb_write_reg(CR91, VIACR, 0x00);
			viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
		}
		break;

	case INTERFACE_DVP1:
		if (set_iga == IGA1)
			viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
		else {
			viafb_write_reg(CR91, VIACR, 0x00);
			viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
		}
		break;

	case INTERFACE_DFP_HIGH:
		if (set_iga == IGA1)
			viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
		else {
			viafb_write_reg(CR91, VIACR, 0x00);
			viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
			viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
		}
		break;

	case INTERFACE_DFP_LOW:
		if (set_iga == IGA1)
			viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
		else {
			viafb_write_reg(CR91, VIACR, 0x00);
			viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
			viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
		}

		break;

	case INTERFACE_DFP:
		if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
		    || (UNICHROME_P4M890 ==
		    viaparinfo->chip_info->gfx_chip_name))
			viafb_write_reg_mask(CR97, VIACR, 0x84,
				       BIT7 + BIT2 + BIT1 + BIT0);
		if (set_iga == IGA1) {
			viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
			viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
		} else {
			viafb_write_reg(CR91, VIACR, 0x00);
			viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
			viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
		}
		break;

	case INTERFACE_LVDS0:
	case INTERFACE_LVDS0LVDS1:
		if (set_iga == IGA1) {
			viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
		} else {
			viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
		}

		break;

	case INTERFACE_LVDS1:
		if (set_iga == IGA1) {
			viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
		} else {
			viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
		}

		break;
	}
}

/* Search Mode Index */
static int search_mode_setting(int ModeInfoIndex)
{
	int i = 0;

	while ((i < NUM_TOTAL_MODETABLE)
	       && (ModeInfoIndex != CLE266Modes[i].ModeIndex)) i++;
	if ((i >= NUM_TOTAL_MODETABLE))
		i = 0;
	return i;

}

struct VideoModeTable *viafb_get_modetbl_pointer(int Index)
{
	struct VideoModeTable *TmpTbl = NULL;
	TmpTbl = &CLE266Modes[search_mode_setting(Index)];
	return (TmpTbl);
}

struct VideoModeTable *viafb_get_cea_mode_tbl_pointer(int Index)
{
	struct VideoModeTable *TmpTbl = NULL;
	int i = 0;
	while ((i < NUM_TOTAL_CEA_MODES)
	       && (Index != CEA_HDMI_Modes[i].ModeIndex)) i++;
	if ((i < NUM_TOTAL_CEA_MODES))
		TmpTbl = &CEA_HDMI_Modes[i];
	 else {
		/*Still use general timing if don't find CEA timing */
		i = 0;
		while ((i < NUM_TOTAL_MODETABLE)
		       && (Index != CLE266Modes[i].ModeIndex))
		       i++;
		if ((i >= NUM_TOTAL_MODETABLE))
			i = 0;
		TmpTbl = &CLE266Modes[i];
	}
	return TmpTbl;
}

static void load_fix_bit_crtc_reg(void)
{
	/* always set to 1 */
	viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
	/* line compare should set all bits = 1 (extend modes) */
	viafb_write_reg(CR18, VIACR, 0xff);
	/* line compare should set all bits = 1 (extend modes) */
	viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
	/* line compare should set all bits = 1 (extend modes) */
	viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
	/* line compare should set all bits = 1 (extend modes) */
	viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
	/* line compare should set all bits = 1 (extend modes) */
	viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
	/*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
	/* extend mode always set to e3h */
	viafb_write_reg(CR17, VIACR, 0xe3);
	/* extend mode always set to 0h */
	viafb_write_reg(CR08, VIACR, 0x00);
	/* extend mode always set to 0h */
	viafb_write_reg(CR14, VIACR, 0x00);

	/* If K8M800, enable Prefetch Mode. */
	if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
		|| (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
		viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
	if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
	    && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
		viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);

}

void viafb_load_reg(int timing_value, int viafb_load_reg_num,
	struct io_register *reg,
	      int io_type)
{
	int reg_mask;
	int bit_num = 0;
	int data;
	int i, j;
	int shift_next_reg;
	int start_index, end_index, cr_index;
	u16 get_bit;

	for (i = 0; i < viafb_load_reg_num; i++) {
		reg_mask = 0;
		data = 0;
		start_index = reg[i].start_bit;
		end_index = reg[i].end_bit;
		cr_index = reg[i].io_addr;

		shift_next_reg = bit_num;
		for (j = start_index; j <= end_index; j++) {
			/*if (bit_num==8) timing_value = timing_value >>8; */
			reg_mask = reg_mask | (BIT0 << j);
			get_bit = (timing_value & (BIT0 << bit_num));
			data =
			    data | ((get_bit >> shift_next_reg) << start_index);
			bit_num++;
		}
		if (io_type == VIACR) {
			viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
		} else {
			viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
		}

	}

}

/* Write Registers */
void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
{
	int i;
	unsigned char RegTemp;

	/*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */

	for (i = 0; i < ItemNum; i++) {
		outb(RegTable[i].index, RegTable[i].port);
		RegTemp = inb(RegTable[i].port + 1);
		RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
		outb(RegTemp, RegTable[i].port + 1);
	}
}

void viafb_load_offset_reg(int h_addr, int bpp_byte, int set_iga)
{
	int reg_value;
	int viafb_load_reg_num;
	struct io_register *reg;

	switch (set_iga) {
	case IGA1_IGA2:
	case IGA1:
		reg_value = IGA1_OFFSET_FORMULA(h_addr, bpp_byte);
		viafb_load_reg_num = offset_reg.iga1_offset_reg.reg_num;
		reg = offset_reg.iga1_offset_reg.reg;
		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
		if (set_iga == IGA1)
			break;
	case IGA2:
		reg_value = IGA2_OFFSET_FORMULA(h_addr, bpp_byte);
		viafb_load_reg_num = offset_reg.iga2_offset_reg.reg_num;
		reg = offset_reg.iga2_offset_reg.reg;
		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
		break;
	}
}

void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
{
	int reg_value;
	int viafb_load_reg_num;
	struct io_register *reg = NULL;

	switch (set_iga) {
	case IGA1_IGA2:
	case IGA1:
		reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
		viafb_load_reg_num = fetch_count_reg.
			iga1_fetch_count_reg.reg_num;
		reg = fetch_count_reg.iga1_fetch_count_reg.reg;
		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
		if (set_iga == IGA1)
			break;
	case IGA2:
		reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
		viafb_load_reg_num = fetch_count_reg.
			iga2_fetch_count_reg.reg_num;
		reg = fetch_count_reg.iga2_fetch_count_reg.reg;
		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
		break;
	}

}

void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
{
	int reg_value;
	int viafb_load_reg_num;
	struct io_register *reg = NULL;
	int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
	    0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
	int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
	    0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;

	if (set_iga == IGA1) {
		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
			iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
			iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
			iga1_fifo_high_threshold =
			    K800_IGA1_FIFO_HIGH_THRESHOLD;
			/* If resolution > 1280x1024, expire length = 64, else
			   expire length = 128 */
			if ((hor_active > 1280) && (ver_active > 1024))
				iga1_display_queue_expire_num = 16;
			else
				iga1_display_queue_expire_num =
				    K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;

		}

		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
			iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
			iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
			iga1_fifo_high_threshold =
			    P880_IGA1_FIFO_HIGH_THRESHOLD;
			iga1_display_queue_expire_num =
			    P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;

			/* If resolution > 1280x1024, expire length = 64, else
			   expire length = 128 */
			if ((hor_active > 1280) && (ver_active > 1024))
				iga1_display_queue_expire_num = 16;
			else
				iga1_display_queue_expire_num =
				    P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
		}

		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
			iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
			iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
			iga1_fifo_high_threshold =
			    CN700_IGA1_FIFO_HIGH_THRESHOLD;

			/* If resolution > 1280x1024, expire length = 64,
			   else expire length = 128 */
			if ((hor_active > 1280) && (ver_active > 1024))
				iga1_display_queue_expire_num = 16;
			else
				iga1_display_queue_expire_num =
				    CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
		}

		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
			iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
			iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
			iga1_fifo_high_threshold =
			    CX700_IGA1_FIFO_HIGH_THRESHOLD;
			iga1_display_queue_expire_num =
			    CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
		}

		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
			iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
			iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
			iga1_fifo_high_threshold =
			    K8M890_IGA1_FIFO_HIGH_THRESHOLD;
			iga1_display_queue_expire_num =
			    K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
		}

		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
			iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
			iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
			iga1_fifo_high_threshold =
			    P4M890_IGA1_FIFO_HIGH_THRESHOLD;
			iga1_display_queue_expire_num =
			    P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
		}

		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
			iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
			iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
			iga1_fifo_high_threshold =
			    P4M900_IGA1_FIFO_HIGH_THRESHOLD;
			iga1_display_queue_expire_num =
			    P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
		}

		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
			iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
			iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
			iga1_fifo_high_threshold =
			    VX800_IGA1_FIFO_HIGH_THRESHOLD;
			iga1_display_queue_expire_num =
			    VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
		}

		/* Set Display FIFO Depath Select */
		reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
		viafb_load_reg_num =
		    display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
		reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);

		/* Set Display FIFO Threshold Select */
		reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
		viafb_load_reg_num =
		    fifo_threshold_select_reg.
		    iga1_fifo_threshold_select_reg.reg_num;
		reg =
		    fifo_threshold_select_reg.
		    iga1_fifo_threshold_select_reg.reg;