hw.c

via framebuffer driver

								     0x10,
								     0x00},
	/* Index 0xC0~0xC3 */
	{0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
								     0x10,
								     0x0C},
	/* Index 0xC4~0xC7 */
	{0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
								     0x04,
								     0x10},
	/* Index 0xC8~0xCB */
	{0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
								     0x08,
								     0x10},
	/* Index 0xCC~0xCF */
	{0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
								     0x08,
								     0x0A},
	/* Index 0xD0~0xD3 */
	{0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
								     0x0E,
								     0x08},
	/* Index 0xD4~0xD7 */
	{0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
								     0x10,
								     0x08},
	/* Index 0xD8~0xDB */
	{0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
								     0x10,
								     0x0E},
	/* Index 0xDC~0xDF */
	{0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
								     0x0A,
								     0x10},
	/* Index 0xE0~0xE3 */
	{0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
								     0x0B,
								     0x10},
	/* Index 0xE4~0xE7 */
	{0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
								     0x0B,
								     0x0C},
	/* Index 0xE8~0xEB */
	{0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
								     0x0F,
								     0x0B},
	/* Index 0xEC~0xEF */
	{0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
								     0x10,
								     0x0B},
	/* Index 0xF0~0xF3 */
	{0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
								     0x10,
								     0x0F},
	/* Index 0xF4~0xF7 */
	{0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
								     0x0C,
								     0x10},
	/* Index 0xF8~0xFB */
	{0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
								     0x00,
								     0x00},
	/* Index 0xFC~0xFF */
	{0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
								     0x00,
								     0x00}
};

static void set_crt_output_path(int set_iga);
static void dvi_patch_skew_dvp0(void);
static void dvi_patch_skew_dvp1(void);
static void dvi_patch_skew_dvp_low(void);
static void set_dvi_output_path(int set_iga, int output_interface);
static void set_lcd_output_path(int set_iga, int output_interface);
static int search_mode_setting(int ModeInfoIndex);
static void load_fix_bit_crtc_reg(void);
static void init_gfx_chip_info(void);
static void init_tmds_chip_info(void);
static void init_lvds_chip_info(void);
static void device_screen_off(void);
static void device_screen_on(void);
static void set_display_channel(void);
static void device_off(void);
static void device_on(void);
static void enable_second_display_channel(void);
static void disable_second_display_channel(void);
static int get_fb_size_from_pci(void);

void viafb_write_reg(u8 index, u16 io_port, u8 data)
{
	outb(index, io_port);
	outb(data, io_port + 1);
	/*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
}
u8 viafb_read_reg(int io_port, u8 index)
{
	outb(index, io_port);
	return (inb(io_port + 1));
}

void viafb_lock_crt(void)
{
	viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
}

void viafb_unlock_crt(void)
{
	viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
	viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
}

void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
{
	u8 tmp;

	outb(index, io_port);
	tmp = inb(io_port + 1);
	outb((data & mask) | (tmp & (~mask)), io_port + 1);
	/*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
}

void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
{
	outb(index, LUT_INDEX_WRITE);
	outb(r, LUT_DATA);
	outb(g, LUT_DATA);
	outb(b, LUT_DATA);
}

/*Set IGA path for each device*/
void viafb_set_iga_path(void)
{

	if (viafb_SAMM_ON == 1) {
		if (viafb_CRT_ON) {
			if (viafb_primary_dev == CRT_Device) {
				viaparinfo->crt_setting_info->iga_path = IGA1;
			} else {
				viaparinfo->crt_setting_info->iga_path = IGA2;
			}
		}

		if (viafb_DVI_ON) {
			if (viafb_primary_dev == DVI_Device) {
				viaparinfo->tmds_setting_info->iga_path = IGA1;
			} else {
				viaparinfo->tmds_setting_info->iga_path = IGA2;
			}
		}

		if (viafb_LCD_ON) {
			if (viafb_primary_dev == LCD_Device) {
				if (viafb_dual_fb &&
					(viaparinfo->chip_info->gfx_chip_name ==
					UNICHROME_CLE266)) {
					viaparinfo->
					lvds_setting_info->iga_path = IGA2;
					viaparinfo->
					crt_setting_info->iga_path = IGA1;
					viaparinfo->
					tmds_setting_info->iga_path = IGA1;
				} else
					viaparinfo->
					lvds_setting_info->iga_path = IGA1;
			} else {
				viaparinfo->lvds_setting_info->iga_path = IGA2;
			}
		}
		if (viafb_LCD2_ON) {
			if (LCD2_Device == viafb_primary_dev) {
				viaparinfo->lvds_setting_info2->iga_path = IGA1;
			} else {
				viaparinfo->lvds_setting_info2->iga_path = IGA2;
			}
		}
	} else {
		viafb_SAMM_ON = 0;

		if (viafb_CRT_ON && viafb_LCD_ON) {
			viaparinfo->crt_setting_info->iga_path = IGA1;
			viaparinfo->lvds_setting_info->iga_path = IGA2;
		} else if (viafb_CRT_ON && viafb_DVI_ON) {
			viaparinfo->crt_setting_info->iga_path = IGA1;
			viaparinfo->tmds_setting_info->iga_path = IGA2;
		} else if (viafb_LCD_ON && viafb_DVI_ON) {
			viaparinfo->tmds_setting_info->iga_path = IGA1;
			viaparinfo->lvds_setting_info->iga_path = IGA2;
		} else if (viafb_LCD_ON && viafb_LCD2_ON) {
			viaparinfo->lvds_setting_info->iga_path = IGA2;
			viaparinfo->lvds_setting_info2->iga_path = IGA2;
		} else if (viafb_CRT_ON) {
			viaparinfo->crt_setting_info->iga_path = IGA1;
		} else if (viafb_LCD_ON) {
			viaparinfo->lvds_setting_info->iga_path = IGA2;
		} else if (viafb_DVI_ON) {
			viaparinfo->tmds_setting_info->iga_path = IGA1;
		}
	}
}

void viafb_set_start_addr(void)
{
	unsigned long offset = 0, tmp = 0, size = 0;
	unsigned long length;

	DEBUG_MSG(KERN_INFO "viafb_set_start_addr!\n");
	viafb_unlock_crt();
	/* update starting address of IGA1 */
	viafb_write_reg(CR0C, VIACR, 0x00);	/*initial starting address */
	viafb_write_reg(CR0D, VIACR, 0x00);
	viafb_write_reg(CR34, VIACR, 0x00);
	viafb_write_reg_mask(CR48, VIACR, 0x00, 0x1F);

	if (viafb_dual_fb) {
		viaparinfo->iga_path = IGA1;
		viaparinfo1->iga_path = IGA2;
	}

	if (viafb_SAMM_ON == 1) {
		if (!viafb_dual_fb) {
			if (viafb_second_size) {
				size = viafb_second_size * 1024 * 1024;
			} else {
				size = 8 * 1024 * 1024;
			}
		} else {

			size = viaparinfo1->memsize;
		}
		offset = viafb_second_offset;
		DEBUG_MSG(KERN_INFO
			  "viafb_second_size=%lx, second start_adddress=%lx\n",
			  size, offset);
	}
	if (viafb_SAMM_ON == 1) {
		offset = offset >> 3;

		tmp = viafb_read_reg(VIACR, 0x62) & 0x01;
		tmp |= (offset & 0x7F) << 1;
		viafb_write_reg(CR62, VIACR, tmp);
		viafb_write_reg(CR63, VIACR, ((offset & 0x7F80) >> 7));
		viafb_write_reg(CR64, VIACR, ((offset & 0x7F8000) >> 15));
		viafb_write_reg(CRA3, VIACR, ((offset & 0x3800000) >> 23));
	} else {
		/* update starting address */
		viafb_write_reg(CR62, VIACR, 0x00);
		viafb_write_reg(CR63, VIACR, 0x00);
		viafb_write_reg(CR64, VIACR, 0x00);
		viafb_write_reg(CRA3, VIACR, 0x00);
	}

	if (viafb_SAMM_ON == 1) {
		if (via_fb_accel) {
			if (!viafb_dual_fb)
				length = size - viaparinfo->fbmem_used;
			else
				length = size - viaparinfo1->fbmem_used;
		} else
			length = size;
		offset = (unsigned long)(void *)viafb_FB_MM +
			viafb_second_offset;
		memset((void *)offset, 0, length);
	}

	viafb_lock_crt();
}

void viafb_set_output_path(int device, int set_iga, int output_interface)
{
	switch (device) {
	case DEVICE_CRT:
		set_crt_output_path(set_iga);
		break;
	case DEVICE_DVI:
		set_dvi_output_path(set_iga, output_interface);
		break;
	case DEVICE_LCD:
		set_lcd_output_path(set_iga, output_interface);
		break;
	}
}

static void set_crt_output_path(int set_iga)
{
	viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);

	switch (set_iga) {
	case IGA1:
		viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
		break;
	case IGA2:
	case IGA1_IGA2:
		viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
		viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
		if (set_iga == IGA1_IGA2)
			viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
		break;
	}
}

static void dvi_patch_skew_dvp0(void)
{
	/* Reset data driving first: */
	viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
	viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);

	switch (viaparinfo->chip_info->gfx_chip_name) {
	case UNICHROME_P4M890:
		{
			if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
				(viaparinfo->tmds_setting_info->v_active ==
				1200))
				viafb_write_reg_mask(CR96, VIACR, 0x03,
					       BIT0 + BIT1 + BIT2);
			else
				viafb_write_reg_mask(CR96, VIACR, 0x07,
					       BIT0 + BIT1 + BIT2);
			break;
		}

	case UNICHROME_P4M900:
		{
			viafb_write_reg_mask(CR96, VIACR, 0x07,
				       BIT0 + BIT1 + BIT2 + BIT3);
			viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
			viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
			break;
		}

	default:
		{
			break;
		}
	}
}

static void dvi_patch_skew_dvp1(void)
{
	switch (viaparinfo->chip_info->gfx_chip_name) {
	case UNICHROME_CX700:
		{
			break;
		}

	default:
		{
			break;
		}
	}
}

static void dvi_patch_skew_dvp_low(void)
{
	switch (viaparinfo->chip_info->gfx_chip_name) {
	case UNICHROME_K8M890:
		{
			viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
			break;
		}

	case UNICHROME_P4M900:
		{
			viafb_write_reg_mask(CR99, VIACR, 0x08,
				       BIT0 + BIT1 + BIT2 + BIT3);
			break;
		}

	case UNICHROME_P4M890:
		{
			viafb_write_reg_mask(CR99, VIACR, 0x0F,
				       BIT0 + BIT1 + BIT2 + BIT3);
			break;
		}

	default:
		{
			break;
		}
	}
}

static void set_dvi_output_path(int set_iga, int output_interface)
{
	switch (output_interface) {
	case INTERFACE_DVP0:
		viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);

		if (set_iga == IGA1) {
			viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
			viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
				BIT5 + BIT7);
		} else {
			viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
			viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
				BIT5 + BIT7);
		}

		viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);

		dvi_patch_skew_dvp0();
		break;

	case INTERFACE_DVP1:
		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
			if (set_iga == IGA1)
				viafb_write_reg_mask(CR93, VIACR, 0x21,
					       BIT0 + BIT5 + BIT7);
			else
				viafb_write_reg_mask(CR93, VIACR, 0xA1,
					       BIT0 + BIT5 + BIT7);
		} else {
			if (set_iga == IGA1)
				viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
			else
				viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
		}

		viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
		dvi_patch_skew_dvp1();
		break;
	case INTERFACE_DFP_HIGH:
		if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
			if (set_iga == IGA1) {
				viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
				viafb_write_reg_mask(CR97, VIACR, 0x03,
					       BIT0 + BIT1 + BIT4);
			} else {
				viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
				viafb_write_reg_mask(CR97, VIACR, 0x13,
					       BIT0 + BIT1 + BIT4);
			}
		}
		viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
		break;