dvi.c

via framebuffer driver

	}

	return ret;
}

/* Query Flat Panel's EDID Table Version Through DVI Connector */
static int viafb_dvi_query_EDID(void)
{
	u8 data0, data1;
	int restore;

	DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n");

	restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
	viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;

	data0 = (u8) tmds_register_read(0x00);
	data1 = (u8) tmds_register_read(0x01);
	if ((data0 == 0) && (data1 == 0xFF)) {
		viaparinfo->chip_info->
			tmds_chip_info.tmds_chip_slave_addr = restore;
		return (EDID_VERSION_1);	/* Found EDID1 Table */
	}

	data0 = (u8) tmds_register_read(0x00);
	viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
	if (data0 == 0x20)
		return (EDID_VERSION_2);	/* Found EDID2 Table */
	else
		return (FALSE);
}

/*
 *
 * int dvi_get_panel_size_from_DDCv1(void)
 *
 *     - Get Panel Size Using EDID1 Table
 *
 * Return Type:    int
 *
 */
static int dvi_get_panel_size_from_DDCv1(void)
{
	int i, max_h = 0, max_v = 0, tmp, restore;
	unsigned char rData;
	unsigned char EDID_DATA[18];

	DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");

	restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
	viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;

	rData = tmds_register_read(0x23);
	if (rData & 0x3C)
		max_h = 640;
	if (rData & 0xC0)
		max_h = 720;
	if (rData & 0x03)
		max_h = 800;

	rData = tmds_register_read(0x24);
	if (rData & 0xC0)
		max_h = 800;
	if (rData & 0x1E)
		max_h = 1024;
	if (rData & 0x01)
		max_h = 1280;

	for (i = 0x25; i < 0x6D; i++) {
		switch (i) {
		case 0x26:
		case 0x28:
		case 0x2A:
		case 0x2C:
		case 0x2E:
		case 0x30:
		case 0x32:
		case 0x34:
			rData = tmds_register_read(i);
			if (rData == 1)
				break;
			/* data = (data + 31) * 8 */
			tmp = (rData + 31) << 3;
			if (tmp > max_h)
				max_h = tmp;
			break;

		case 0x36:
		case 0x48:
		case 0x5A:
		case 0x6C:
			tmds_register_read_bytes(i, EDID_DATA, 10);
			if (!(EDID_DATA[0] || EDID_DATA[1])) {
				/* The first two byte must be zero. */
				if (EDID_DATA[3] == 0xFD) {
					/* To get max pixel clock. */
					viaparinfo->tmds_setting_info->
					max_pixel_clock = EDID_DATA[9] * 10;
				}
			}
			break;

		default:
			break;
		}
	}

	switch (max_h) {
	case 640:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_640X480;
		break;
	case 800:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_800X600;
		break;
	case 1024:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1024X768;
		break;
	case 1280:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1280X1024;
		break;
	case 1400:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1400X1050;
		break;
	case 1440:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1440X1050;
		break;
	case 1600:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1600X1200;
		break;
	case 1920:
		if (max_v == 1200) {
			viaparinfo->tmds_setting_info->dvi_panel_size =
				VIA_RES_1920X1200;
		} else {
			viaparinfo->tmds_setting_info->dvi_panel_size =
				VIA_RES_1920X1080;
		}

		break;
	default:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1024X768;
		DEBUG_MSG(KERN_INFO "Unknow panel size max resolution = %d !\
					 set default panel size.\n", max_h);
		break;
	}

	DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
		  viaparinfo->tmds_setting_info->max_pixel_clock);
	viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
	return viaparinfo->tmds_setting_info->dvi_panel_size;
}

/*
 *
 * int dvi_get_panel_size_from_DDCv2(void)
 *
 *     - Get Panel Size Using EDID2 Table
 *
 * Return Type:    int
 *
 */
static int dvi_get_panel_size_from_DDCv2(void)
{
	int HSize = 0, restore;
	unsigned char R_Buffer[2];

	DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv2 \n");

	restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
	viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA2;

	/* Horizontal: 0x76, 0x77 */
	tmds_register_read_bytes(0x76, R_Buffer, 2);
	HSize = R_Buffer[0];
	HSize += R_Buffer[1] << 8;

	switch (HSize) {
	case 640:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_640X480;
		break;
	case 800:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_800X600;
		break;
	case 1024:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1024X768;
		break;
	case 1280:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1280X1024;
		break;
	case 1400:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1400X1050;
		break;
	case 1440:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1440X1050;
		break;
	case 1600:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1600X1200;
		break;
	default:
		viaparinfo->tmds_setting_info->dvi_panel_size =
			VIA_RES_1024X768;
		DEBUG_MSG(KERN_INFO "Unknow panel size max resolution = %d!\
					set default panel size.\n", HSize);
		break;
	}

	viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
	return viaparinfo->tmds_setting_info->dvi_panel_size;
}

/*
 *
 * unsigned char dvi_get_panel_info(void)
 *
 *     - Get Panel Size
 *
 * Return Type:    unsigned char
 */
static unsigned char dvi_get_panel_info(void)
{
	DEBUG_MSG(KERN_INFO "dvi_get_panel_info! \n");

	viafb_dvi_sense();
	switch (viafb_dvi_query_EDID()) {
	case 1:
		dvi_get_panel_size_from_DDCv1();
		break;
	case 2:
		dvi_get_panel_size_from_DDCv2();
		break;
	default:
		break;
	}

	DEBUG_MSG(KERN_INFO "dvi panel size is %2d \n",
		  viaparinfo->tmds_setting_info->dvi_panel_size);
	return (unsigned char)(viaparinfo->tmds_setting_info->dvi_panel_size);
}

/* If Disable DVI, turn off pad */
void viafb_dvi_disable(void)
{
	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_DVP0)
		viafb_write_reg(SR1E, VIASR,
		viafb_read_reg(VIASR, SR1E) & (~0xC0));

	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_DVP1)
		viafb_write_reg(SR1E, VIASR,
		viafb_read_reg(VIASR, SR1E) & (~0x30));

	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_DFP_HIGH)
		viafb_write_reg(SR2A, VIASR,
		viafb_read_reg(VIASR, SR2A) & (~0x0C));

	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_DFP_LOW)
		viafb_write_reg(SR2A, VIASR,
		viafb_read_reg(VIASR, SR2A) & (~0x03));

	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_TMDS)
		/* Turn off TMDS power. */
		viafb_write_reg(CRD2, VIACR,
		viafb_read_reg(VIACR, CRD2) | 0x08);
}

/* If Enable DVI, turn off pad */
void viafb_dvi_enable(void)
{
	u8 data;

	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_DVP0) {
		viafb_write_reg(SR1E, VIASR,
			viafb_read_reg(VIASR, SR1E) | 0xC0);
		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
			tmds_register_write(0x88, 0x3b);
		else
			/*clear CR91[5] to direct on display period
			   in the secondary diplay path */
			viafb_write_reg(CR91, VIACR,
			viafb_read_reg(VIACR, CR91) & 0xDF);
	}

	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_DVP1) {
		viafb_write_reg(SR1E, VIASR,
			viafb_read_reg(VIASR, SR1E) | 0x30);

		/*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
		if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
			tmds_register_write(0x88, 0x3b);
		} else {
			/*clear CR91[5] to direct on display period
			  in the secondary diplay path */
			viafb_write_reg(CR91, VIACR,
			viafb_read_reg(VIACR, CR91) & 0xDF);
		}

		/*fix DVI cannot enable on EPIA-M board */
		if (viafb_platform_epia_dvi == 1) {
			viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
			viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
			if (via_bus_width == 24) {
				if (viafb_device_lcd_dualedge == 1)
					data = 0x3F;
				else
					data = 0x37;
				viafb_i2cWriteByte(viaparinfo->chip_info->
					     tmds_chip_info.
					     tmds_chip_slave_addr,
					     0x08, data);
			}
		}
	}

	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_DFP_HIGH) {
		viafb_write_reg(SR2A, VIASR,
			viafb_read_reg(VIASR, SR2A) | 0x0C);
		viafb_write_reg(CR91, VIACR,
			viafb_read_reg(VIACR, CR91) & 0xDF);
	}

	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_DFP_LOW) {
		viafb_write_reg(SR2A, VIASR,
			viafb_read_reg(VIASR, SR2A) | 0x03);
		viafb_write_reg(CR91, VIACR,
			viafb_read_reg(VIACR, CR91) & 0xDF);
	}
	if (viaparinfo->chip_info->
		tmds_chip_info.output_interface == INTERFACE_TMDS) {
		/* Turn on Display period in the panel path. */
		viafb_write_reg_mask(CR91, VIACR, 0, BIT7);

		/* Turn on TMDS power. */
		viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
	}
}