lcd.c

via framebuffer driver

static void fill_lcd_format(void)
{
	u8 bdithering = 0, bdual = 0;

	if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
		bdual = BIT4;
	if (viaparinfo->lvds_setting_info->LCDDithering)
		bdithering = BIT0;
	/* Dual & Dithering */
	viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
}

static void check_diport_of_integrated_lvds(
	struct lvds_chip_information *plvds_chip_info,
				     struct lvds_setting_information
				     *plvds_setting_info)
{
	/* Determine LCD DI Port by hardware layout. */
	switch (viafb_display_hardware_layout) {
	case HW_LAYOUT_LCD_ONLY:
		{
			if (plvds_setting_info->device_lcd_dualedge) {
				plvds_chip_info->output_interface =
				    INTERFACE_LVDS0LVDS1;
			} else {
				plvds_chip_info->output_interface =
				    INTERFACE_LVDS0;
			}

			break;
		}

	case HW_LAYOUT_DVI_ONLY:
		{
			plvds_chip_info->output_interface = INTERFACE_NONE;
			break;
		}

	case HW_LAYOUT_LCD1_LCD2:
	case HW_LAYOUT_LCD_EXTERNAL_LCD2:
		{
			plvds_chip_info->output_interface =
			    INTERFACE_LVDS0LVDS1;
			break;
		}

	case HW_LAYOUT_LCD_DVI:
		{
			plvds_chip_info->output_interface = INTERFACE_LVDS1;
			break;
		}

	default:
		{
			plvds_chip_info->output_interface = INTERFACE_LVDS1;
			break;
		}
	}

	DEBUG_MSG(KERN_INFO
		  "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
		  viafb_display_hardware_layout,
		  plvds_chip_info->output_interface);
}

void viafb_init_lvds_output_interface(struct lvds_chip_information
				*plvds_chip_info,
				struct lvds_setting_information
				*plvds_setting_info)
{
	if (INTERFACE_NONE != plvds_chip_info->output_interface) {
		/*Do nothing, lcd port is specified by module parameter */
		return;
	}

	switch (plvds_chip_info->lvds_chip_name) {

	case VT1636_LVDS:
		switch (viaparinfo->chip_info->gfx_chip_name) {
		case UNICHROME_CX700:
			plvds_chip_info->output_interface = INTERFACE_DVP1;
			break;
		case UNICHROME_CN700:
			plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
			break;
		default:
			plvds_chip_info->output_interface = INTERFACE_DVP0;
			break;
		}
		break;

	case INTEGRATED_LVDS:
		check_diport_of_integrated_lvds(plvds_chip_info,
						plvds_setting_info);
		break;

	default:
		switch (viaparinfo->chip_info->gfx_chip_name) {
		case UNICHROME_K8M890:
		case UNICHROME_P4M900:
		case UNICHROME_P4M890:
			plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
			break;
		default:
			plvds_chip_info->output_interface = INTERFACE_DFP;
			break;
		}
		break;
	}
}

static struct display_timing lcd_centering_timging(struct display_timing
					    mode_crt_reg,
					    struct display_timing panel_crt_reg)
{
	struct display_timing crt_reg;

	crt_reg.hor_total = panel_crt_reg.hor_total;
	crt_reg.hor_addr = mode_crt_reg.hor_addr;
	crt_reg.hor_blank_start =
	    (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
	    crt_reg.hor_addr;
	crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
	crt_reg.hor_sync_start =
	    (panel_crt_reg.hor_sync_start -
	     panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
	crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;

	crt_reg.ver_total = panel_crt_reg.ver_total;
	crt_reg.ver_addr = mode_crt_reg.ver_addr;
	crt_reg.ver_blank_start =
	    (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
	    crt_reg.ver_addr;
	crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
	crt_reg.ver_sync_start =
	    (panel_crt_reg.ver_sync_start -
	     panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
	crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;

	return crt_reg;
}

static void load_crtc_shadow_timing(struct display_timing mode_timing,
			     struct display_timing panel_timing)
{
	struct io_register *reg = NULL;
	int i;
	int viafb_load_reg_Num = 0;
	int reg_value = 0;

	if (viaparinfo->lvds_setting_info->display_method == LCD_EXPANDSION) {
		/* Expansion */
		for (i = 12; i < 20; i++) {
			switch (i) {
			case H_TOTAL_SHADOW_INDEX:
				reg_value =
				    IGA2_HOR_TOTAL_SHADOW_FORMULA
				    (panel_timing.hor_total);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.hor_total_shadow.
				    reg_num;
				reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
				break;
			case H_BLANK_END_SHADOW_INDEX:
				reg_value =
				    IGA2_HOR_BLANK_END_SHADOW_FORMULA
				    (panel_timing.hor_blank_start,
				     panel_timing.hor_blank_end);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.
				    hor_blank_end_shadow.reg_num;
				reg =
				    iga2_shadow_crtc_reg.
				    hor_blank_end_shadow.reg;
				break;
			case V_TOTAL_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_TOTAL_SHADOW_FORMULA
				    (panel_timing.ver_total);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.ver_total_shadow.
				    reg_num;
				reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
				break;
			case V_ADDR_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_ADDR_SHADOW_FORMULA
				    (panel_timing.ver_addr);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.ver_addr_shadow.
				    reg_num;
				reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
				break;
			case V_BLANK_SATRT_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_BLANK_START_SHADOW_FORMULA
				    (panel_timing.ver_blank_start);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.
				    ver_blank_start_shadow.reg_num;
				reg =
				    iga2_shadow_crtc_reg.
				    ver_blank_start_shadow.reg;
				break;
			case V_BLANK_END_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_BLANK_END_SHADOW_FORMULA
				    (panel_timing.ver_blank_start,
				     panel_timing.ver_blank_end);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.
				    ver_blank_end_shadow.reg_num;
				reg =
				    iga2_shadow_crtc_reg.
				    ver_blank_end_shadow.reg;
				break;
			case V_SYNC_SATRT_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_SYNC_START_SHADOW_FORMULA
				    (panel_timing.ver_sync_start);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.
				    ver_sync_start_shadow.reg_num;
				reg =
				    iga2_shadow_crtc_reg.
				    ver_sync_start_shadow.reg;
				break;
			case V_SYNC_END_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_SYNC_END_SHADOW_FORMULA
				    (panel_timing.ver_sync_start,
				     panel_timing.ver_sync_end);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.
				    ver_sync_end_shadow.reg_num;
				reg =
				    iga2_shadow_crtc_reg.
				    ver_sync_end_shadow.reg;
				break;
			}
			viafb_load_reg(reg_value,
				viafb_load_reg_Num, reg, VIACR);
		}
	} else {		/* Centering */
		for (i = 12; i < 20; i++) {
			switch (i) {
			case H_TOTAL_SHADOW_INDEX:
				reg_value =
				    IGA2_HOR_TOTAL_SHADOW_FORMULA
				    (panel_timing.hor_total);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.hor_total_shadow.
				    reg_num;
				reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
				break;
			case H_BLANK_END_SHADOW_INDEX:
				reg_value =
				    IGA2_HOR_BLANK_END_SHADOW_FORMULA
				    (panel_timing.hor_blank_start,
				     panel_timing.hor_blank_end);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.
				    hor_blank_end_shadow.reg_num;
				reg =
				    iga2_shadow_crtc_reg.
				    hor_blank_end_shadow.reg;
				break;
			case V_TOTAL_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_TOTAL_SHADOW_FORMULA
				    (panel_timing.ver_total);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.ver_total_shadow.
				    reg_num;
				reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
				break;
			case V_ADDR_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_ADDR_SHADOW_FORMULA
				    (mode_timing.ver_addr);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.ver_addr_shadow.
				    reg_num;
				reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
				break;
			case V_BLANK_SATRT_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_BLANK_START_SHADOW_FORMULA
				    (mode_timing.ver_blank_start);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.
				    ver_blank_start_shadow.reg_num;
				reg =
				    iga2_shadow_crtc_reg.
				    ver_blank_start_shadow.reg;
				break;
			case V_BLANK_END_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_BLANK_END_SHADOW_FORMULA
				    (panel_timing.ver_blank_start,
				     panel_timing.ver_blank_end);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.
				    ver_blank_end_shadow.reg_num;
				reg =
				    iga2_shadow_crtc_reg.
				    ver_blank_end_shadow.reg;
				break;
			case V_SYNC_SATRT_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_SYNC_START_SHADOW_FORMULA(
				    (panel_timing.ver_sync_start -
				    panel_timing.ver_blank_start) +
				    (panel_timing.ver_addr -
				    mode_timing.ver_addr) / 2 +
				    mode_timing.ver_addr);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.ver_sync_start_shadow.
				    reg_num;
				reg =
				    iga2_shadow_crtc_reg.ver_sync_start_shadow.
				    reg;
				break;
			case V_SYNC_END_SHADOW_INDEX:
				reg_value =
				    IGA2_VER_SYNC_END_SHADOW_FORMULA(
				    (panel_timing.ver_sync_start -
				    panel_timing.ver_blank_start) +
				    (panel_timing.ver_addr -
				    mode_timing.ver_addr) / 2 +
				    mode_timing.ver_addr,
				    panel_timing.ver_sync_end);
				viafb_load_reg_Num =
				    iga2_shadow_crtc_reg.ver_sync_end_shadow.
				    reg_num;
				reg =
				    iga2_shadow_crtc_reg.ver_sync_end_shadow.
				    reg;
				break;
			}
			viafb_load_reg(reg_value,
				viafb_load_reg_Num, reg, VIACR);
		}
	}
}

bool viafb_lcd_get_mobile_state(bool *mobile)
{
	unsigned char *romptr, *tableptr;
	u8 core_base;
	unsigned char *biosptr;
	/* Rom address */
	u32 romaddr = 0x000C0000;
	u16 start_pattern = 0;

	biosptr = ioremap(romaddr, 0x10000);

	memcpy(&start_pattern, biosptr, 2);
	/* Compare pattern */
	if (start_pattern == 0xAA55) {
		/* Get the start of Table */
		/* 0x1B means BIOS offset position */
		romptr = biosptr + 0x1B;
		tableptr = biosptr + *((u16 *) romptr);

		/* Get the start of biosver structure */
		/* 18 means BIOS version position. */
		romptr = tableptr + 18;
		romptr = biosptr + *((u16 *) romptr);

		/* The offset should be 44, but the
		   actual image is less three char. */
		/* pRom += 44; */
		romptr += 41;

		core_base = *romptr++;

		if (core_base & 0x8) {
			*mobile = FALSE;
		} else {
			*mobile = TRUE;
		}
		/* release memory */
		iounmap(biosptr);

		return TRUE;
	} else {
		iounmap(biosptr);
		return FALSE;
	}
}

static void viafb_load_scaling_factor_for_p4m900(int set_hres,
	int set_vres, int panel_hres, int panel_vres)
{
	int h_scaling_factor;
	int v_scaling_factor;
	u8 cra2 = 0;
	u8 cr77 = 0;
	u8 cr78 = 0;
	u8 cr79 = 0;
	u8 cr9f = 0;
	/* Check if expansion for horizontal */
	if (set_hres < panel_hres) {
		/* Load Horizontal Scaling Factor */

		/* For VIA_K8M800 or later chipsets. */
		h_scaling_factor =
		    K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
		/* HSCaleFactor[1:0] at CR9F[1:0] */
		cr9f = h_scaling_factor & 0x0003;
		/* HSCaleFactor[9:2] at CR77[7:0] */
		cr77 = (h_scaling_factor & 0x03FC) >> 2;
		/* HSCaleFactor[11:10] at CR79[5:4] */
		cr79 = (h_scaling_factor & 0x0C00) >> 10;
		cr79 <<= 4;

		/* Horizontal scaling enabled */
		cra2 = 0xC0;

		DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d\n",
			  h_scaling_factor);
	} else {
		/* Horizontal scaling disabled */
		cra2 = 0x00;
	}

	/* Check if expansion for vertical */
	if (set_vres < panel_vres) {
		/* Load Vertical Scaling Factor */

		/* For VIA_K8M800 or later chipsets. */
		v_scaling_factor =
		    K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);

		/* Vertical scaling enabled */
		cra2 |= 0x08;
		/* VSCaleFactor[0] at CR79[3] */
		cr79 |= ((v_scaling_factor & 0x0001) << 3);
		/* VSCaleFactor[8:1] at CR78[7:0] */
		cr78 |= (v_scaling_factor & 0x01FE) >> 1;
		/* VSCaleFactor[10:9] at CR79[7:6] */
		cr79 |= ((v_scaling_factor & 0x0600) >> 9) << 6;

		DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d\n",
			  v_scaling_factor);
	} else {
		/* Vertical scaling disabled */
		cra2 |= 0x00;
	}

	viafb_write_reg_mask(CRA2, VIACR, cra2, BIT3 + BIT6 + BIT7);
	viafb_write_reg_mask(CR77, VIACR, cr77, 0xFF);
	viafb_write_reg_mask(CR78, VIACR, cr78, 0xFF);
	viafb_write_reg_mask(CR79, VIACR, cr79, 0xF8);
	viafb_write_reg_mask(CR9F, VIACR, cr9f, BIT0 + BIT1);
}