📄 tda8007_routines.c
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{
AUXR = INT_XRAM;
P15 = 1;
#ifndef UCRD
if(Tx_pointer<buffer_length) // buffer_length needs to be 256
ch = data_exch_buff[Tx_pointer++];
else
ch = exceed_buff[Tx_pointer++];
#else
ch = data_exch_buff[Tx_pointer++];
#endif
AUXR = EXT_XRAM;
P15 = 0;
Tx_counter --;
Get_One_Byte = 0;
}
user_byte = *ptr_msr; //update MSR register
TX_mode = (*ptr_ucr1 & 0x08);
if(alarm == card_selected) //alarm on working card
{ //wayout in case of parity error
gen_flag = 0;
gen_flag = 1;
P15 = 1;
AUXR = INT_XRAM;
return(!OK);
}
}while((MSR_TBE==0)&& TX_mode); //wait for transmit one byte
if(card_comm_error==TX_ERR_PARITY) //if no parity error then proceed next byte
{
gen_flag = 0;
gen_flag = 1;
gen_flag = 0;
gen_flag = 1;
P15 = 1;
AUXR = INT_XRAM;
return(!OK);
}
Get_One_Byte = 1;
}while(Tx_counter);
if (protocol_type==1)
{
// load timers with CWT value in T=1
*ptr_tor1 = (uchar)(CWT);
*ptr_tor2 = (uchar)(CWT>>8);
*ptr_tor3 = 0;
}
P15 = 1;
AUXR = INT_XRAM;
return(OK);
}
void load_timers(uchar value_TOR3,uchar value_TOR2,uchar value_TOR1)
{
write_register(TOR3,value_TOR3);
write_register(TOR2,value_TOR2);
write_register(TOR1,value_TOR1);
}
/*****************************************************************/
void start_timers(uchar mode, uchar tor3, uchar tor2, uchar tor1)
{
load_timers(tor3, tor2, tor1);
write_register(TOC, mode); // start timers
}
bit flag_UX;
bit flag_T15;
bit flag_T14;
uchar active_card(unsigned int ptr,uchar V3_V5)
{
unsigned int i;
uchar nb_hist;
uchar value;
bit fSetBaudRate=1;
write_bit(RIU,0);
write_bit(RIU,1);
write_bit(SAN, 0);
write_bit(TXRX, 0);
write_bit(DIS_AUX, 1);
write_bit(DIS_TXRX, 1);
flag_ATR = 0;
end_APDU = 0;
flag_APDU = 0;
flag_ATR_error = 0;
if(V3_V5 == V3) //power on 3V or 5V
write_bit(V3V5,1);
else
write_bit(V3V5,0);
write_register(FCR, 0x07); // setting 1 parity error and fifo = 8
synchro = 0;
deactive = 0;
set_baud_rate_2(0x11, 0, 0); //default FiDi
set_clock_card(0x02); //xtal/4
flag_timer3 = 0;
write_bit(RSTIN,0);
if(!check_pres_card())
{
card_comm_error = CARD_ABSENT;
return(0);
}
if(emv)
start_timers(0x65, 0x00, 0x6C, 0xC0); // 19200 ETU's with T1, T2+3: soft for 108 etus
else
start_timers(0x61, 0x00, 0x6C, 0xC0); // T1 stop, T2+3: soft for 108
flag_FiDi_error = 0;
card_comm_error = 0;
alarm = 0;
count_rep = 0;
T0_accept = OK;
T1_accept = 0;
flag_T15 = 0;
flag_T14 = 0;
TA2_flag = 0;
flag_TB1 = 0;
flag_TB3 = 0;
flag0 = 0;
flag1 = 0;
flag2 = 0;
Rblock_flag = 0;
flag_UX = 0;
has_replied = 0;
ifsc = ifsd = 32; // TA2 default value
old_ifsc = 32;
protocol_type = PROT_T0;
asser_mode_flag = 0;
write_bit(PROT,PROT_T0);
write_bit(AUTOCN,0);
write_bit(SS,1);
TA2 = 0;
TC1 = 0;
WI = 10;
WTX = 1;
BWI = 4; // BWI = 4 par defaut (28.11.00)
CWT = 8203; //CWI = 13 par defaut
UX = 1; //Classe 5V, Clock stop not supported
nb_last_bytes_ATR = 2; // at least TS + T0
End_ATR = 0;
RestartTimerSoft = 1;
nb_loop1 = 100; // 100 * 192 = 19200;
// counter2 + 3 SW are used to check 9600 ETUs between each byte
// counter1 Auto is used to check 19200 ETUs of ATR
// --> counter 2 & 3 are SW triggered (MODE2 = 2)
// --> counter 1 is in autoreload mode (MODE1 = 1)
write_bit(START,1); // VCC ON
while(flag_timer3==0)
{
if(alarm)
return(0); // wait for 108 etus count
} // before rising RST
flag_timer3 = 0;
flag_ATR = 1;
empty_fifo();
write_bit(RSTIN,1);
if(emv)
start_timers(0x65, 0x00, 0x78, 0xC0); // 19200 ETU's with T1, T2+3: soft
else // for 108 + 12 etus
start_timers(0x61, 0x00, 0x78, 0xC0); // T1 stop, T2+3: soft for 108 + 12 etus
if ( rcv_card(1,ptr) != OK) // receive TS
return(0);
// CAREFUL!
// With the C2 version, we do not need to reset SS bit within UCR1 and
// we must not change AUTOC\ bit within UCR2
checksum = 0; // checksum is calculated from TO to TCK not include
if (rcv_card(1,ptr+1) != OK) //receive T0
return(0);
process_nb_bytes_ATR(data_exch_buff[ptr+1]); // compute T0
nb_hist = data_exch_buff[ptr+1] & 0x0F; // nb of historical bytes
if(nb_hist)
flag0 = 1;
nb_last_bytes_ATR += nb_hist;
// if only one byte to receive then setting EATR
if(nb_last_bytes_ATR==1)
{
write_bit(EATR, 1);
End_ATR = 0;
RestartTimerSoft = 0;
nb_last_bytes_ATR = 0;
}
i = process_ATR(data_exch_buff[ptr+1],ptr+2);
// after process_ATR() we should receive historical bytes and eventually TCK.
End_ATR = 1;
if((i == 0xFF))
{
flag0 = 0;
return(0);
}
i = i + 2; // TS, T0
if( TA2_flag ==1) // if TA2 present then specific mode
{
if( (protocol_type != 0) && (protocol_type != 1) )
{
card_comm_error = NO_T0_NO_T1;
return(0);
}
}
// If T=0 and flag_T15 or flag_T14 present then ATR contains a TCK,
// if T=1 then ATR always contains a TCK
// ================================================================
if( ((T0_accept == 1) && ((flag_T15 == 1)||(flag_T14 == 1))) || (T1_accept == 1) )
{
nb_hist++; // adding one more byte for TCK
if(flag0) // if yet done in process_nb_bytes_ATR()
nb_last_bytes_ATR ++;
}
if(nb_hist==0)
stop_timers();
if(rcv_card(nb_last_bytes_ATR, ptr+i) != OK) //receive TCK
return(0);
flag_ATR = 0;
i = i + nb_hist;
if(flag_ATR_error == 1)
return(0);
write_bit(PROT,PROT_T0);
// Checking checksum if present ((T=0 with flag_T15 or flag_T14) or (T=1))
// ===========================
if( ((T0_accept == 1) && ((flag_T15 == 1)||(flag_T14 == 1))) || (T1_accept == 1) )
{
if( checksum != 0)
{
card_comm_error = CHECKSUM_ERROR;
deactive = 1;
return(0);
}
}
if( (T0_accept == 0) && (T1_accept == 0) )
{
card_comm_error = NO_T0_NO_T1;
return(0);
}
value = data_exch_buff[ptr];
// if error in specific mode then return error
if((flag_FiDi_error==1) && TA2_flag)
{
card_comm_error = BAD_FiDi;
flag_FiDi_error = 0;
return(0);
}
if( !((value == 0x3F) || (value == 0x3B)) )
{
card_comm_error = TS_ERROR;
deactive = 1;
return(0);
}
if((T1_accept == OK) && (T0_accept != OK) )
{
if((flag_TB3 == 0)&&(emv))
{
card_comm_error = TB3_ABSENT;
return(0);
}
protocol_type = PROT_T1;
write_bit(PROT,PROT_T1);
}
else
{
protocol_type = PROT_T0;
write_bit(PROT,PROT_T0);
}
if(TA2_flag == 1) //then specific mode
{
if( protocol_type == PROT_T1)
{
if((flag_TB3 == 0)&&(emv))
{
deactive = 1;
card_comm_error = TB3_ABSENT;
return(0);
}
T1_accept = OK;
T0_accept = !OK;
write_bit(PROT,PROT_T1);
}
else
{
if( (TA2 & 0x0F) == PROT_T0)
T0_accept = OK;
if( (TA2 & 0x10) != 0 )
{
card_comm_error =WRONG_b5_TA2; //b5 de TA2 egal 1
return(0);
}
}
if( (T1_accept != OK) && (T0_accept != OK) )
{
card_comm_error = NO_T0_NO_T1;
return(0);
}
if(set_baud_rate_2(FiDi, 0, 0) != OK) //specific mode so setting FiDi
{
//FiDi not accepted
card_comm_error = PARAM_ERROR;
return(0);
}
fSetBaudRate = 0; // 28/11/00
}
if(emv)
{
if(!flag_warm_reset)
{
if((flag_TB1 == 0) )
{
card_comm_error = TB1_NOT_PRESENT;
return(0);
}
if((TB1 != 0 ) )
{
card_comm_error = TB1_NOT_ZERO;
return(0);
}
}
}
set_guard_time(TC1);
if (fSetBaudRate)
{
set_BWT(0x11);
WWT = (960 * WI) + 1;
}
return(i);
}
void init_system(unsigned int length)
{
uchar card;
buffer_length = length;
write_bit(RIU, 0);
write_bit(RIU, 1);
// card 3 do not have PCR register
select_card(2); //select card 2 reset 礐
write_register(PCR, 0xF0); //dectivate card 2
select_card(1); //select card 1
write_register(PCR, 0xF0); //deactivate card 1
write_register(FCR,0x07); //FIFO size = 8 compteur d'erreurs de parit⌨️ 快捷键说明
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