dsp2802x_sysctrl.h

Piccolo TMS320F2802x头文件

// TI File $Revision: /main/4 $
// Checkin $Date: October 3, 2008   10:56:57 $
//###########################################################################
//
// FILE:   DSP2802x_SysCtrl.h
//
// TITLE:  DSP2802x Device System Control Register Definitions.
//
//###########################################################################
// $TI Release: 2802x Header Files V1.00 $
// $Release Date: November 10, 2008 $
//###########################################################################

#ifndef DSP2802x_SYS_CTRL_H
#define DSP2802x_SYS_CTRL_H

#ifdef __cplusplus
extern "C" {
#endif

//---------------------------------------------------------------------------
// System Control Individual Register Bit Definitions:
//

// XCLKOUT Control
struct XCLK_BITS   {    // bits  description
   Uint16 XCLKOUTDIV:2; // 1:0   XCLKOUT Divide Ratio
   Uint16 rsvd1:3;      // 4:2   reserved
   Uint16 rsvd2:1;      // 5     reserved
   Uint16 XCLKINSEL:1;  // 6     XCLKIN Source Select bit
   Uint16 rsvd3:9;     // 15:7   reserved
};

union XCLK_REG {
   Uint16                     all;
   struct XCLK_BITS           bit;
};

// PLL Status Register
struct PLLSTS_BITS   {    // bits  description
   Uint16 PLLLOCKS:1;     // 0     PLL lock status
   Uint16 rsvd1:1;        // 1     reserved
   Uint16 PLLOFF:1;       // 2     PLL off bit
   Uint16 MCLKSTS:1;      // 3     Missing clock status bit
   Uint16 MCLKCLR:1;      // 4     Missing clock clear bit
   Uint16 OSCOFF:1;       // 5     Oscillator clock off
   Uint16 MCLKOFF:1;      // 6     Missing clock detect
   Uint16 DIVSEL:2;       // 8:7   Divide select (/4 default)
   Uint16 rsvd2:6;        // 14:9  reserved
   Uint16 NORMRDYE:1;     // 15    VREG NORMRDY enable bit
};

union PLLSTS_REG {
   Uint16                     all;
   struct PLLSTS_BITS         bit;
};

// Clock Control Register
struct CLKCTL_BITS   {        // bits  description
   Uint16 OSCCLKSRCSEL:1;     // 0     Oscillator clock source select bit
   Uint16 OSCCLKSRC2SEL:1;    // 1     Oscillator 2 clock source select bit
   Uint16 WDCLKSRCSEL:1;      // 2     Watchdog clock source select bit
   Uint16 TMR2CLKSRCSEL:2;    // 4:3   CPU timer 2 clock source select bit
   Uint16 TMR2CLKPRESCALE:3;  // 7:5   CPU timer 2 clock pre-scale value
   Uint16 INTOSC1OFF:1;       // 8     Internal oscillator off bit
   Uint16 INTOSC1HALTI:1;     // 9     Internal oscillator 1 halt mode ignore bit
   Uint16 INTOSC2OFF:1;       // 10    Internal oscillator 2 off bit
   Uint16 INTOSC2HALTI:1;     // 11    Internal oscillator 2 halt mode ignore bit
   Uint16 WDHALTI:1;          // 12    Watchdog halt mode ignore bit
   Uint16 XCLKINOFF:1;        // 13    XCLKIN off bit
   Uint16 XTALOSCOFF:1;       // 14    Crystal (External) oscillator off bit
   Uint16 NMIRESETSEL:1;      // 15    NMI reset select bit
};

union CLKCTL_REG {
   Uint16                     all;
   struct CLKCTL_BITS         bit;
};

// Internal Oscillator 1 Trim
struct INTOSC1TRIM_BITS   {    // bits  description
   Uint16 COARSETRIM:8;        // 7:0   8-bit coarse trim value
   Uint16 rsvd1:1;             // 8     reserved
   Uint16 FINETRIM:6;          // 9:14  6-bit fine trim value
   Uint16 rsvd2:1;             // 15    reserved
};

union INTOSC1TRIM_REG {
   Uint16                     all;
   struct INTOSC1TRIM_BITS    bit;
};

// Internal Oscillator 2 Trim
struct INTOSC2TRIM_BITS   {    // bits  description
   Uint16 COARSETRIM:8;        // 7:0   8-bit coarse trim value
   Uint16 rsvd1:1;             // 8     reserved
   Uint16 FINETRIM:6;          // 9:14  6-bit fine trim value
   Uint16 rsvd2:1;             // 15    reserved
};

union INTOSC2TRIM_REG {
   Uint16                     all;
   struct INTOSC2TRIM_BITS    bit;
};

// Low speed peripheral clock register bit definitions:
struct LOSPCP_BITS  {   // bits  description
   Uint16 LSPCLK:3;     // 2:0   Rate relative to SYSCLKOUT
   Uint16 rsvd1:13;     // 15:3  reserved
};

union LOSPCP_REG {
   Uint16                     all;
   struct LOSPCP_BITS         bit;
};

// Peripheral clock control register 0 bit definitions:
struct PCLKCR0_BITS  {  // bits  description
   Uint16 HRPWMENCLK:1; // 0     Enable low speed clk to HRPWM
   Uint16 rsvd1:1;      // 1     reserved
   Uint16 TBCLKSYNC:1;  // 2     ETWPM Module TBCLK enable/sync
   Uint16 ADCENCLK:1;   // 3     Enable high speed clk to ADC
   Uint16 I2CAENCLK:1;  // 4     Enable SYSCLKOUT to I2C-A
   Uint16 rsvd2:3;      // 7:5   reserved
   Uint16 SPIAENCLK:1;  // 8     Enable low speed clk to SPI-A
   Uint16 rsvd3:1;      // 9     reserved
   Uint16 SCIAENCLK:1;  // 10    Enable low speed clk to SCI-A
   Uint16 rsvd4:5;      // 15:11 reserved

};

union PCLKCR0_REG {
   Uint16                     all;
   struct PCLKCR0_BITS        bit;
};

// Peripheral clock control register 1 bit definitions:
struct PCLKCR1_BITS  {    // bits  description
   Uint16 EPWM1ENCLK:1;   // 0     Enable SYSCLKOUT to EPWM1
   Uint16 EPWM2ENCLK:1;   // 1     Enable SYSCLKOUT to EPWM2
   Uint16 EPWM3ENCLK:1;   // 2     Enable SYSCLKOUT to EPWM3
   Uint16 EPWM4ENCLK:1;   // 3     Enable SYSCLKOUT to EPWM4
   Uint16 rsvd1:4;        // 7:4   reserved
   Uint16 ECAP1ENCLK:1;   // 8     Enable SYSCLKOUT to ECAP1
   Uint16 rsvd2:7;        // 15:9  reserved
};

union PCLKCR1_REG {
   Uint16                     all;
   struct PCLKCR1_BITS        bit;
};

// Peripheral clock control register 3 bit definitions:
struct PCLKCR3_BITS  {       // bits  description
   Uint16 COMP1ENCLK:1;      // 0     Enable SYSCLKOUT to COMP1
   Uint16 COMP2ENCLK:1;      // 1     Enable SYSCLKOUT to COMP2
   Uint16 rsvd1:1;           // 2     reserved
   Uint16 rsvd2:5;           // 7:3   reserved
   Uint16 CPUTIMER0ENCLK:1;  // 8     Enable SYSCLKOUT to CPUTIMER0
   Uint16 CPUTIMER1ENCLK:1;  // 9     Enable SYSCLKOUT to CPUTIMER1
   Uint16 CPUTIMER2ENCLK:1;  // 10    Enable SYSCLKOUT to CPUTIMER2
   Uint16 rsvd3:2;           // 12:11 reserved
   Uint16 GPIOINENCLK:1;     // 13    Enable SYSCLKOUT to GPIO
   Uint16 rsvd4:2;           // 15:14
};

union PCLKCR3_REG {
   Uint16              all;
   struct PCLKCR3_BITS bit;
};

// PLL control register bit definitions:
struct PLLCR_BITS {      // bits  description
   Uint16 DIV:4;         // 3:0   Set clock ratio for the PLL
   Uint16 rsvd1:12;      // 15:4  reserved
};

union PLLCR_REG {
   Uint16             all;
   struct PLLCR_BITS  bit;
};

// Low Power Mode 0 control register bit definitions:
struct LPMCR0_BITS {     // bits  description
   Uint16 LPM:2;         // 1:0   Set the low power mode
   Uint16 QUALSTDBY:6;   // 7:2   Qualification
   Uint16 rsvd1:7;       // 14:8  reserved
   Uint16 WDINTE:1;      // 15    Enables WD to wake the device from STANDBY
};

union LPMCR0_REG {
   Uint16              all;
   struct LPMCR0_BITS  bit;
};

// JTAG Debug Register
struct JTAGDEBUG_BITS {     // bits  description
   Uint16 JTAGDIS:1;        // 0     JTAG Port Disable Bit
   Uint16 rsvd1:15;         // 15:1  reserved
};

union JTAGDEBUG_REG {
	Uint16                all;
	struct JTAGDEBUG_BITS bit;
};


//---------------------------------------------------------------------------
// System Control Register File:
//