📄 dsp2802x_epwm.h
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//----------------------------------------------------
// Event trigger pre-scale register bit definitions */
struct ETPS_BITS { // bits description
Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select
Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register
Uint16 rsvd1:4; // 7:4 reserved
Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select
Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register
Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select
Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register
};
union ETPS_REG {
Uint16 all;
struct ETPS_BITS bit;
};
//----------------------------------------------------
// Event trigger Flag register bit definitions */
struct ETFLG_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Flag
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Flag
Uint16 SOCB:1; // 3 EPWMxSOCB Flag
Uint16 rsvd2:12; // 15:4 reserved
};
union ETFLG_REG {
Uint16 all;
struct ETFLG_BITS bit;
};
//----------------------------------------------------
// Event trigger Clear register bit definitions */
struct ETCLR_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Clear
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Clear
Uint16 SOCB:1; // 3 EPWMxSOCB Clear
Uint16 rsvd2:12; // 15:4 reserved
};
union ETCLR_REG {
Uint16 all;
struct ETCLR_BITS bit;
};
//----------------------------------------------------
// Event trigger Force register bit definitions */
struct ETFRC_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Force
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Force
Uint16 SOCB:1; // 3 EPWMxSOCB Force
Uint16 rsvd2:12; // 15:4 reserved
};
union ETFRC_REG {
Uint16 all;
struct ETFRC_BITS bit;
};
//----------------------------------------------------
// PWM chopper control register bit definitions */
struct PCCTL_BITS { // bits description
Uint16 CHPEN:1; // 0 PWM chopping enable
Uint16 OSHTWTH:4; // 4:1 One-shot pulse width
Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency
Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle
Uint16 rsvd1:5; // 15:11 reserved
};
union PCCTL_REG {
Uint16 all;
struct PCCTL_BITS bit;
};
//----------------------------------------------------
// Enhanced Trip register bit definitions */
struct DCTRIPSEL_BITS { // bits description
Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High, COMP Input Select
Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low, COMP Input Select
Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High, COMP Input Select
Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low, COMP Input Select
};
union DCTRIPSEL_REG {
Uint16 all;
struct DCTRIPSEL_BITS bit;
};
struct DCCTL_BITS { // bits description
Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal Select
Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Cynchronization Signal Select
Uint16 EVT1SOCE:1; // 2 DCEVT1 SOC, Enable/Disable
Uint16 EVT1SYNCE:1; // 3 DCEVT1 Sync, Enable/Disable
Uint16 rsvd1:4; // 7:4 reserved
Uint16 EVT2SRCSEL:1; // 8 DCEVT2 Source Signal Select
Uint16 EVT2FRCSYNCSEL:1; // 9 DCEVT2 Force Synchronization Signal Select
Uint16 rsvd2:6; // 15:10 reserved
};
union DCCTL_REG {
Uint16 all;
struct DCCTL_BITS bit;
};
struct DCCAPCTL_BITS { // bits description
Uint16 CAPE:1; // 0 Counter Capture Enable/Disable
Uint16 SHDWMODE:1; // 1 Counter Capture Mode
Uint16 rsvd:14; // 15:2 reserved
};
union DCCAPCTL_REG {
Uint16 all;
struct DCCAPCTL_BITS bit;
};
struct DCFCTL_BITS { // bits description
Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select
Uint16 BLANKE:1; // 2 Blanking Enable/Disable
Uint16 BLANKINV:1; // 3 Blanking Window Inversion
Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment
Uint16 rsvd:10; // 15:6 reserved
};
union DCFCTL_REG {
Uint16 all;
struct DCFCTL_BITS bit;
};
//----------------------------------------------------
// High resolution period control register bit definitions */
struct HRPCTL_BITS { // bits description
Uint16 HRPE:1; // 0 High resolution period enable
Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select Bit
Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable Bit
Uint16 rsvd1:13; // 15:3 reserved
};
union HRPCTL_REG {
Uint16 all;
struct HRPCTL_BITS bit;
};
//----------------------------------------------------
// High Resolution Register bit definitions */
struct HRCNFG_BITS { // bits description
Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits
Uint16 CTLMODE:1; // 2 Control mode Select Bit
Uint16 HRLOAD:2; // 4:3 Shadow mode Select Bit
Uint16 SELOUTB:1; // 5 EPWMB Output Select Bit
Uint16 AUTOCONV:1; // 6 Autoconversion Bit
Uint16 SWAPAB:1; // 7 Swap EPWMA & EPWMB Outputs Bit
Uint16 rsvd1:8; // 15:8 reserved
};
union HRCNFG_REG {
Uint16 all;
struct HRCNFG_BITS bit;
};
struct HRPWR_BITS { // bits description
Uint16 rsvd1:6; // 5:0 reserved
Uint16 MEPOFF:4; // 9:6 MEP Calibration Off Bits
Uint16 rsvd2:6; // 15:10 reserved
};
union HRPWR_REG {
Uint16 all;
struct HRPWR_BITS bit;
};
struct TBPHS_HRPWM_REG { // bits description
Uint16 TBPHSHR; // 15:0 Extension register for HRPWM Phase (8 bits)
Uint16 TBPHS; // 31:16 Phase offset register
};
union TBPHS_HRPWM_GROUP {
Uint32 all;
struct TBPHS_HRPWM_REG half;
};
struct CMPA_HRPWM_REG { // bits description
Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits)
Uint16 CMPA; // 31:16 Compare A reg
};
union CMPA_HRPWM_GROUP {
Uint32 all;
struct CMPA_HRPWM_REG half;
};
struct TBPRD_HRPWM_REG { // bits description
Uint16 TBPRDHR; // 15:0 Extension register for HRPWM Period (8 bits)
Uint16 TBPRD; // 31:16 Timebase Period Register
};
union TBPRD_HRPWM_GROUP {
Uint32 all;
struct TBPRD_HRPWM_REG half;
};
struct EPWM_REGS {
union TBCTL_REG TBCTL; // Time Base Control Register
union TBSTS_REG TBSTS; // Time Base Status Register
union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR
Uint16 TBCTR; // Time Base Counter
Uint16 TBPRD; // Time Base Period register set
Uint16 TBPRDHR; // Time Base Period High Res Register
union CMPCTL_REG CMPCTL; // Compare control
union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR
Uint16 CMPB; // Compare B reg
union AQCTL_REG AQCTLA; // Action qual output A
union AQCTL_REG AQCTLB; // Action qual output B
union AQSFRC_REG AQSFRC; // Action qual SW force
union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force
union DBCTL_REG DBCTL; // Dead-band control
Uint16 DBRED; // Dead-band rising edge delay
Uint16 DBFED; // Dead-band falling edge delay
union TZSEL_REG TZSEL; // Trip zone select
union TZDCSEL_REG TZDCSEL; // Trip zone digital comparator select
union TZCTL_REG TZCTL; // Trip zone control
union TZEINT_REG TZEINT; // Trip zone interrupt enable
union TZFLG_REG TZFLG; // Trip zone interrupt flags
union TZCLR_REG TZCLR; // Trip zone clear
union TZFRC_REG TZFRC; // Trip zone force interrupt
union ETSEL_REG ETSEL; // Event trigger selection
union ETPS_REG ETPS; // Event trigger pre-scaler
union ETFLG_REG ETFLG; // Event trigger flags
union ETCLR_REG ETCLR; // Event trigger clear
union ETFRC_REG ETFRC; // Event trigger force
union PCCTL_REG PCCTL; // PWM chopper control
Uint16 rsvd3;
union HRCNFG_REG HRCNFG; // HRPWM Config Reg
union HRPWR_REG HRPWR; // HRPWM Power Register
Uint16 rsvd4[4];
Uint16 HRMSTEP; // HRPWM MEP Step Register
Uint16 rsvd5;
union HRPCTL_REG HRPCTL; // High Resolution Period Control
Uint16 rsvd6;
union TBPRD_HRPWM_GROUP TBPRDM; // Union of TBPRD:TBPRDHR mirror registers
union CMPA_HRPWM_GROUP CMPAM; // Union of CMPA:CMPAHR mirror registers
Uint16 rsvd7[2];
union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select
union DCCTL_REG DCACTL; // Digital Compare A Control
union DCCTL_REG DCBCTL; // Digital Compare B Control
union DCFCTL_REG DCFCTL; // Digital Compare Filter Control
union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control
Uint16 DCFOFFSET; // Digital Compare Filter Offset
Uint16 DCFOFFSETCNT;// Digital Compare Filter Offset Counter
Uint16 DCFWINDOW; // Digital Compare Filter Window
Uint16 DCFWINDOWCNT;// Digital Compare Filter Window Counter
Uint16 DCCAP; // Digital Compare Filter Counter Capture
};
//---------------------------------------------------------------------------
// External References & Function Declarations:
//
extern volatile struct EPWM_REGS EPwm1Regs;
extern volatile struct EPWM_REGS EPwm2Regs;
extern volatile struct EPWM_REGS EPwm3Regs;
extern volatile struct EPWM_REGS EPwm4Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2802x_EPWM_H definition
//===========================================================================
// End of file.
//===========================================================================
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