📄 dsp2802x_epwm.h
字号:
// TI File $Revision: /main/5 $
// Checkin $Date: October 3, 2008 10:43:15 $
//###########################################################################
//
// FILE: DSP2802x_EPWM.h
//
// TITLE: DSP2802x Enhanced PWM Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: 2802x Header Files V1.00 $
// $Release Date: November 10, 2008 $
//###########################################################################
#ifndef DSP2802x_EPWM_H
#define DSP2802x_EPWM_H
#ifdef __cplusplus
extern "C" {
#endif
//----------------------------------------------------
// Time base control register bit definitions */
struct TBCTL_BITS { // bits description
Uint16 CTRMODE:2; // 1:0 Counter Mode
Uint16 PHSEN:1; // 2 Phase load enable
Uint16 PRDLD:1; // 3 Active period load
Uint16 SYNCOSEL:2; // 5:4 Sync output select
Uint16 SWFSYNC:1; // 6 Software force sync pulse
Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale
Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale
Uint16 PHSDIR:1; // 13 Phase Direction
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union TBCTL_REG {
Uint16 all;
struct TBCTL_BITS bit;
};
//----------------------------------------------------
// Time base status register bit definitions */
struct TBSTS_BITS { // bits description
Uint16 CTRDIR:1; // 0 Counter direction status
Uint16 SYNCI:1; // 1 External input sync status
Uint16 CTRMAX:1; // 2 Counter max latched status
Uint16 rsvd1:13; // 15:3 reserved
};
union TBSTS_REG {
Uint16 all;
struct TBSTS_BITS bit;
};
//----------------------------------------------------
// Compare control register bit definitions */
struct CMPCTL_BITS { // bits description
Uint16 LOADAMODE:2; // 0:1 Active compare A
Uint16 LOADBMODE:2; // 3:2 Active compare B
Uint16 SHDWAMODE:1; // 4 Compare A block operating mode
Uint16 rsvd1:1; // 5 reserved
Uint16 SHDWBMODE:1; // 6 Compare B block operating mode
Uint16 rsvd2:1; // 7 reserved
Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status
Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status
Uint16 rsvd3:6; // 15:10 reserved
};
union CMPCTL_REG {
Uint16 all;
struct CMPCTL_BITS bit;
};
//----------------------------------------------------
// Action qualifier register bit definitions */
struct AQCTL_BITS { // bits description
Uint16 ZRO:2; // 1:0 Action Counter = Zero
Uint16 PRD:2; // 3:2 Action Counter = Period
Uint16 CAU:2; // 5:4 Action Counter = Compare A up
Uint16 CAD:2; // 7:6 Action Counter = Compare A down
Uint16 CBU:2; // 9:8 Action Counter = Compare B up
Uint16 CBD:2; // 11:10 Action Counter = Compare B down
Uint16 rsvd:4; // 15:12 reserved
};
union AQCTL_REG {
Uint16 all;
struct AQCTL_BITS bit;
};
//----------------------------------------------------
// Action qualifier SW force register bit definitions */
struct AQSFRC_BITS { // bits description
Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked
Uint16 OTSFA:1; // 2 One-time SW Force A output
Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked
Uint16 OTSFB:1; // 5 One-time SW Force A output
Uint16 RLDCSF:2; // 7:6 Reload from Shadow options
Uint16 rsvd1:8; // 15:8 reserved
};
union AQSFRC_REG {
Uint16 all;
struct AQSFRC_BITS bit;
};
//----------------------------------------------------
// Action qualifier continuous SW force register bit definitions */
struct AQCSFRC_BITS { // bits description
Uint16 CSFA:2; // 1:0 Continuous Software Force on output A
Uint16 CSFB:2; // 3:2 Continuous Software Force on output B
Uint16 rsvd1:12; // 15:4 reserved
};
union AQCSFRC_REG {
Uint16 all;
struct AQCSFRC_BITS bit;
};
//----------------------------------------------------
// Dead-band generator control register bit definitions
struct DBCTL_BITS { // bits description
Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control
Uint16 POLSEL:2; // 3:2 Polarity Select Control
Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control
Uint16 rsvd1:9; // 14:4 reserved
Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable
};
union DBCTL_REG {
Uint16 all;
struct DBCTL_BITS bit;
};
//----------------------------------------------------
// Trip zone select register bit definitions
struct TZSEL_BITS { // bits description
Uint16 CBC1:1; // 0 TZ1 CBC select
Uint16 CBC2:1; // 1 TZ2 CBC select
Uint16 CBC3:1; // 2 TZ3 CBC select
Uint16 CBC4:1; // 3 TZ4 CBC select
Uint16 CBC5:1; // 4 TZ5 CBC select
Uint16 CBC6:1; // 5 TZ6 CBC select
Uint16 DCAEVT2:1; // 6 DCAEVT2
Uint16 DCBEVT2:1; // 7 DCBEVT2
Uint16 OSHT1:1; // 8 One-shot TZ1 select
Uint16 OSHT2:1; // 9 One-shot TZ2 select
Uint16 OSHT3:1; // 10 One-shot TZ3 select
Uint16 OSHT4:1; // 11 One-shot TZ4 select
Uint16 OSHT5:1; // 12 One-shot TZ5 select
Uint16 OSHT6:1; // 13 One-shot TZ6 select
Uint16 DCAEVT1:1; // 14 DCAEVT1
Uint16 DCBEVT1:1; // 15 DCBEVT1
};
union TZSEL_REG {
Uint16 all;
struct TZSEL_BITS bit;
};
//----------------------------------------------------
// Trip zone digital compare event select register
struct TZDCSEL_BITS { // bits description
Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1
Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2
Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1
Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2
};
union TZDCSEL_REG {
Uint16 all;
struct TZDCSEL_BITS bit;
};
//----------------------------------------------------
// Trip zone control register bit definitions */
struct TZCTL_BITS { // bits description
Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA
Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB
Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1
Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2
Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1
Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2
Uint16 rsvd:4; // 15:12 reserved
};
union TZCTL_REG {
Uint16 all;
struct TZCTL_BITS bit;
};
//----------------------------------------------------
// Trip zone control register bit definitions */
struct TZEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable
Uint16 OST:1; // 2 Trip Zones One Shot Int Enable
Uint16 DCAEVT1:1; // 3 Force DCAEVT1 event
Uint16 DCAEVT2:1; // 4 Force DCAEVT2 event
Uint16 DCBEVT1:1; // 5 Force DCBEVT1 event
Uint16 DCBEVT2:1; // 6 Force DCBEVT2 event
Uint16 rsvd2:9; // 15:7 reserved
};
union TZEINT_REG {
Uint16 all;
struct TZEINT_BITS bit;
};
//----------------------------------------------------
// Trip zone flag register bit definitions */
struct TZFLG_BITS { // bits description
Uint16 INT:1; // 0 Global status
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 DCAEVT1:1; // 3 Force DCAEVT1 event
Uint16 DCAEVT2:1; // 4 Force DCAEVT2 event
Uint16 DCBEVT1:1; // 5 Force DCBEVT1 event
Uint16 DCBEVT2:1; // 6 Force DCBEVT2 event
Uint16 rsvd2:9; // 15:7 reserved
};
union TZFLG_REG {
Uint16 all;
struct TZFLG_BITS bit;
};
//----------------------------------------------------
// Trip zone flag clear register bit definitions */
struct TZCLR_BITS { // bits description
Uint16 INT:1; // 0 Global status
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 DCAEVT1:1; // 3 Force DCAEVT1 event
Uint16 DCAEVT2:1; // 4 Force DCAEVT2 event
Uint16 DCBEVT1:1; // 5 Force DCBEVT1 event
Uint16 DCBEVT2:1; // 6 Force DCBEVT2 event
Uint16 rsvd2:9; // 15:7 reserved
};
union TZCLR_REG {
Uint16 all;
struct TZCLR_BITS bit;
};
//----------------------------------------------------
// Trip zone flag force register bit definitions */
struct TZFRC_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 DCAEVT1:1; // 3 Force DCAEVT1 event
Uint16 DCAEVT2:1; // 4 Force DCAEVT2 event
Uint16 DCBEVT1:1; // 5 Force DCBEVT1 event
Uint16 DCBEVT2:1; // 6 Force DCBEVT2 event
Uint16 rsvd2:9; // 15:7 reserved
};
union TZFRC_REG {
Uint16 all;
struct TZFRC_BITS bit;
};
//----------------------------------------------------
// Event trigger select register bit definitions */
struct ETSEL_BITS { // bits description
Uint16 INTSEL:3; // 2:0 EPWMxINTn Select
Uint16 INTEN:1; // 3 EPWMxINTn Enable
Uint16 rsvd1:4; // 7:4 reserved
Uint16 SOCASEL:3; // 10:8 Start of conversion A Select
Uint16 SOCAEN:1; // 11 Start of conversion A Enable
Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select
Uint16 SOCBEN:1; // 15 Start of conversion B Enable
};
union ETSEL_REG {
Uint16 all;
struct ETSEL_BITS bit;
};
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -